READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications. - Lucas Bragança da Silva; Ricardo S. Ferreira 001; Michael Canesche; Marcelo M. Menezes; Maria D. Vieira; Jeronimo Costa Penha; Peter Jamieson; José Augusto Miranda Nacif (ACM Trans. Embed. Comput. Syst., 2019)

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays. - Maria D. Vieira; Michael Canesche; Lucas Bragança; Josué Campos; Mateus Silva; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (ISCAS, 2021)

Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots. - Maria D. Vieira; Samuel S. H. Ng; Marcel Walter; Robert Wille; Konrad Walus; Ricardo S. Ferreira 001; Omar P. Vilela Neto; José Augusto Miranda Nacif (IEEE Des. Test, 2022)

Robustness Analysis of Atomic Silicon Quantum Dot Logic Gates. - Arthur M. Fortini; João Gabriel O. Bicalho; Omar P. Vilela Neto; Maria D. Vieira; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (SBCCI, 2024)