A new method for the state reduction of incompletely specified finite sequential machines. - Maria J. Avedillo; José M. Quintana; José Luis Huertas (EURO-DAC, 1990)

Easily Testable PLA-based FSMS. - Maria J. Avedillo; José M. Quintana; José L. Huertas (ISCAS, 1993)

Optimum PLA folding through boolean satisfiability. - José M. Quintana; Maria J. Avedillo; Maria P. Parra; José L. Huertas (ASP-DAC, 1995)

Constrained state assignment of easily testable FSMs. - Maria J. Avedillo; José M. Quintana; José Luis Huertas (J. Electron. Test., 1995)

A Dynamic Model for the State Assignment Problem. - Manuel Martínez; Maria J. Avedillo; José M. Quintana; José L. Huertas (DATE, 1998)

An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. - Manuel Martínez; Maria J. Avedillo; José M. Quintana; José L. Huertas (DATE, 1999)

vMOS-based sorters for multiplier implementations. - Esther Rodríguez-Villegas; Maria J. Avedillo; José M. Quintana; Gloria Huertas; Adoración Rueda (ISCAS (1), 1999)

Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. - José M. Quintana; Maria J. Avedillo; Esther Rodríguez-Villegas; Adoración Rueda (SBCCI, 2000)

νMOS-based Sorter for Arithmetic Applications. - Esther Rodríguez-Villegas; Maria J. Avedillo; José M. Quintana; Gloria Huertas; Adoración Rueda (VLSI Design, 2000)

Two-Criterial Constraint-Driven FSM State Encoding for Low Power. - Manfred Koegst; Steffen Rülke; Günter Franke; Maria J. Avedillo (DSD, 2001)

Practical low-cost CPL implementations threshold logic functions. - José M. Quintana; Maria J. Avedillo; Raúl Jiménez; Esther Rodríguez-Villegas (ACM Great Lakes Symposium on VLSI, 2001)

Low-power logic styles for full-adder circuits. - José M. Quintana; Maria J. Avedillo; Raúl Jiménez; Esther Rodríguez-Villegas (ICECS, 2001)

Reed-Muller descriptions of symmetric functions. - José M. Quintana; Maria J. Avedillo (ISCAS (4), 2001)

Efficient Realization of a Threshold Voter for Self-Purging Redundancy. - José M. Quintana; Maria J. Avedillo; José Luis Huertas (J. Electron. Test., 2001)

An Encoding Technique for Low Power CMOS Implementations of Controllers. - Manuel Martínez; Maria J. Avedillo; José M. Quintana; H. Süß; Manfred Koegst (DATE, 2002)

Threshold-logic-based design of compressors. - José M. Quintana; Maria J. Avedillo; Esther Rodríguez-Villegas; Adoración Rueda (ICECS, 2002)

Simple parallel weighted order statistic filter implementations. - Maria J. Avedillo; José M. Quintana; Esther Rodríguez-Villegas (ISCAS (4), 2002)

Simplified Reed-Muller expressions for residue threshold functions. - José M. Quintana; Maria J. Avedillo; José L. Huertas (ISCAS (4), 2002)

High-speed low-power logic gates using floating gates. - Esther Rodríguez-Villegas; José M. Quintana; Maria J. Avedillo; Adoración Rueda (ISCAS (5), 2002)

COPAS: A New Algorithm for the Partial Input Encoding Problem. - Manuel Martínez; Maria José Avedillo; José M. Quintana; José Luis Huertas (VLSI Design, 2002)

Review of Capacitive Threshold Gate Implementations. - Valeriu Beiu; Maria J. Avedillo; José M. Quintana (ICANN, 2003)

Review of Differential Threshold Gate Implementations. - Valeriu Beiu; José M. Quintana; Maria J. Avedillo (Neural Networks and Computational Intelligence, 2003)

VLSI implementations of threshold logic-a comprehensive survey. - Valeriu Beiu; José M. Quintana; Maria J. Avedillo (IEEE Trans. Neural Networks, 2003)

A Threshold Logic Synthesis Tool for RTD Circuits. - Maria J. Avedillo; José M. Quintana (DSD, 2004)

RTD-based compact programmable gates. - José M. Quintana; Maria J. Avedillo; Héctor Pettenghi (IJCNN, 2004)

Programmable logic gate based on resonant tunnelling devices. - José M. Quintana; Maria J. Avedillo; Héctor Pettenghi (ISCAS (3), 2004)

Pass-transistor based implementations of threshold logic gates for WOS filtering. - Maria J. Avedillo; José M. Quintana; Raúl Jiménez-Naharro (Microelectron. J., 2004)

A Practical Parallel Architecture for Stacks Filters. - Maria J. Avedillo; José M. Quintana; Hamid El Alami; Antonio Jiménez-Calderón (J. VLSI Signal Process., 2004)

Logic Models Supporting the Design of MOBILE-based RTD Circuits. - Maria J. Avedillo; José M. Quintana; Héctor Pettenghi (ASAP, 2005)

Robust frequency divider based on resonant tunneling devices. - Maria J. Avedillo; José M. Quintana; José L. Huertas (ISCAS (3), 2005)

Analysis of frequency divider RTD circuits. - José M. Quintana; Maria J. Avedillo (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Design Guides for a Correct DC Operation in RTD-based Threshold Gates. - José M. Quintana; Maria J. Avedillo; Juan Núñez 002 (DSD, 2006)

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. - David Bol; Jean-Didier Legat; José M. Quintana; Maria José Avedillo (ICECS, 2006)

Limits to a Correct Evaluation in RTD-based Ternary Inverters. - Juan Núñez 002; José M. Quintana; Maria José Avedillo (ICECS, 2006)

Self-latching operation limits for MOBILE circuits. - José M. Quintana; Maria J. Avedillo; Héctor Pettenghi (ISCAS, 2006)

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. - Maria J. Avedillo; José M. Quintana; Héctor Pettenghi Roldán (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Correct operation in SMOBILE-based quasi-differential quantizers. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ECCTD, 2007)

Operation limits in RTD-based ternary quantizers. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ACM Great Lakes Symposium on VLSI, 2007)

Non Return Mobile Logic Family. - Héctor Pettenghi; Maria J. Avedillo; José M. Quintana (ISCAS, 2007)

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ISMVL, 2007)

A quasi-differential quantizer based on SMOBILE. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (SBCCI, 2007)

Analysis of the critical rise time in MOBILE-based circuits. - José M. Quintana; Maria J. Avedillo (ICECS, 2008)

Limits to a correct operation in RTD-based ternary inverters. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ISCAS, 2008)

A novel contribution to the RTD-based threshold logic family. - Héctor Pettenghi; Maria J. Avedillo; José M. Quintana (ISCAS, 2008)

Using multi-threshold threshold gates in RTD-based logic design: A case study. - Héctor Pettenghi; Maria J. Avedillo; José M. Quintana (Microelectron. J., 2008)

Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ISCAS, 2009)

Operation Limits for RTD-Based MOBILE Circuits. - José M. Quintana; Maria J. Avedillo; Juan Núñez 002; Héctor Pettenghi (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Evaluation of RTD-CMOS Logic Gates. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (DSD, 2010)

Single phase MOS-NDR mobile networks. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (ISCAS, 2010)

An improved RNS generator 2n +/- k based on threshold logic. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa; Maria J. Avedillo (VLSI-SoC, 2010)

Efficient realization of RTD-CMOS logic gates. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (ACM Great Lakes Symposium on VLSI, 2011)

Bifurcation diagrams in MOS-NDR frequency divider circuits. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (ICECS, 2012)

Compact and Power Efficient MOS-NDR Muller C-Elements. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (DoCEIS, 2012)

Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (PATMOS, 2012)

Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (DSD, 2013)

Novel pipeline architectures based on Negative Differential Resistance devices. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (Microelectron. J., 2013)

DOE based high-performance gate-level pipelines. - Juan Núñez 002; Maria J. Avedillo; Hector J. Quintero (PATMOS, 2014)

Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Impact of pipeline in the power performance of tunnel transistor circuits. - Maria J. Avedillo; Juan Núñez 002 (PATMOS, 2016)

Exploring logic architectures suitable for TFETs devices. - Juan Núñez 002; Maria J. Avedillo (ISCAS, 2017)

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. - Hector J. Quintero; Manuel Jiménez Través; Maria J. Avedillo; Juan Núñez 002 (SMACD, 2018)

Impact of the RT-level architecture on the power performance of tunnel transistor circuits. - Maria J. Avedillo; Juan Núñez 002 (Int. J. Circuit Theory Appl., 2018)

Power and Speed Evaluation of Hyper-FET Circuits. - Juan Núñez 002; Maria J. Avedillo (IEEE Access, 2019)

Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks. - Jafar Shamsi; Maria José Avedillo; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona (DCIS, 2020)

An Approach to the Device-Circuit Co-Design of HyperFET Circuits. - Manuel Jiménez Través; Juan Núñez 002; Maria José Avedillo (ISCAS, 2020)

Insights Into the Dynamics of Coupled VO2 Oscillators for ONNs. - Juan Núñez 002; José M. Quintana; Maria José Avedillo; Manuel Jiménez Través; Aida Todri-Sanial; Elisabetta Corti; Siegfried F. Karg; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. - Manuel Jiménez Través; Maria José Avedillo; Juan Núñez 002; Bernabé Linares-Barranco (DCIS, 2022)

Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. - Juan Núñez 002; Simon Thomann; Hussam Amrouch; Maria J. Avedillo (ICECS 2022, 2022)

Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4. - Madeleine Abernot; Thierry Gil; Evgenii Kurylin; Tanguy Hardelin; Alexandre Magueresse; Théophile Gonos; Manuel Jiménez Través; Maria José Avedillo; Aida Todri-Sanial (IJCNN, 2022)

How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. - Aida Todri-Sanial; Stefania Carapezzi; Corentin Delacour; Madeleine Abernot; Thierry Gil; Elisabetta Corti; Siegfried F. Karg; Juan Núñez 002; Manuel Jiménez Través; Maria J. Avedillo; Bernabé Linares-Barranco (IEEE Trans. Neural Networks Learn. Syst., 2022)

Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. - Juan Núñez 002; Maria J. Avedillo; Manuel Jiménez Través (SMACD, 2023)

Effect of Device Mismatches in Differential Oscillatory Neural Networks. - Jafar Shamsi; Maria José Avedillo; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Operating Coupled VO₂-Based Oscillators for Solving Ising Models. - Maria J. Avedillo; Manuel Jiménez Través; Corentin Delacour; Aida Todri-Sanial; Bernabé Linares-Barranco; Juan Núñez 002 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)