Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM. - Pavel Poliakov; Ankur Anchlia; Marie Garcia Bardon; Bram Rooseleer; Bart De Wachter; Nadine Collaert; Koen van der Zanden; Wim Dehaene; Diederik Verkest; Miguel Corbalan Miranda (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. - Doyoung Jang; Marie Garcia Bardon; Dmitry Yakimets; Kenichi Miyaguchi; An De Keersgieter; Thomas Chiarella; Romain Ritzenthaler; Morin Dehan; Abdelkarim Mercha (ESSDERC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. - Marie Garcia Bardon; P. Schuddinck; Praveen Raghavan; Doyoung Jang; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. - Halil Kükner; Pieter Weckx; Sébastien Morrison; Jacopo Franco; Maria Toledano-Luque; Moonju Cho; Praveen Raghavan; Ben Kaczer; Doyoung Jang; Kenichi Miyaguchi; Marie Garcia Bardon; Francky Catthoor; et al. (Microprocess. Microsystems, 2015)

5nm: Has the time for a device change come? - Praveen Raghavan; Marie Garcia Bardon; Peter Debacker; P. Schuddinck; Doyoung Jang; Rogier Baert; Diederik Verkest; Aaron Voon-Yew Thean (ISQED, 2016)

Understanding the memory window in 1T-FeFET memories: a depolarization field perspective. - K. Kaczmarek; Marie Garcia Bardon; Y. Xiang; Laurent Breuil; Nicolo Ronchi; Bertrand Parvais; Guido Groeseneken; Jan Van Houdt (IMW, 2021)

Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications. - Mohit Gupta 004; Manu Perumkunnil; Andrea Fantini; Saeideh Alinezhad Chamazcoti; Woojin Kim; Marie Garcia Bardon; Gouri Sankar Kar; Arnaud Furnémont (ESSDERC, 2022)

STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes. - Fernando García-Redondo; S. Rao; M. Gupta; Manu Perumkunnil; Y. Xiang; D. Abdi; Simon Van Beek; Sebastien Couet; Marie Garcia Bardon (ESSDERC, 2023)

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. - S. Yang; Pieter Schuddinck; Marie Garcia Bardon; Yang Xiang; Anabela Veloso; B. T. Chan; Gioele Mirabelli; Gaspard Hiblot; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2023)

A DTCO Framework for 3D NAND Flash Readout. - Mattia Gerardi; Arvind Sharma; Yang Xiang; Jakub Kaczmarek; Fernando García-Redondo; Maarten Rosmeulen; Marie Garcia Bardon (DATE, 2024)

Automatic Regression Framework for MRAM Compact Models Calibration including Stochasticity. - Pierre Graindorge; Bowen Wang; Marie Garcia Bardon; Fernando García-Redondo (SMACD, 2024)

DTCO for Fast STT-MRAM Periphery Operation. - Ahmed Hossam-Eldeen; Bowen Wang; Priyanka Pandey; Marie Garcia Bardon; Fernando García-Redondo (SMACD, 2024)

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. - Hsiao-Hsuan Liu; Carlo Gilardi; Shairfe Muhammad Salahuddin; Zhenlin Pei; Pieter Schuddinck; Yang Xiang; Pieter Weckx; Geert Hellings; Marie Garcia Bardon; Julien Ryckaert; Chenyun Pan; Subhasish Mitra; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

3D IGZO Charge-Coupled Memory DTCO & STCO Analysis for Compute-near-Memory Applications. - Bowen Wang; Khakim Akhunov; Hyungrock Oh; Fernando García-Redondo; Yukai Chen; Arvind Sharma; Jiacong Sun; Sahan Gamage; Maarten Rosmeulen; Swaraj Bandhu Mahato; Rishabh Kishore; Subhali Subhechha; et al. (ISCAS, 2025)

Live Demonstration: N2 Nanosheet Pathfinding-PDK. - Chaohan Wang; Jack Cousins; Anita Farokhnejad; Marie Garcia Bardon; Julien Ryckaert (ISCAS, 2025)

SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study. - Yang Xiang; Fernando García-Redondo; Arvind Sharma; Van Dai Nguyen; Andrea Fantini; Philippe Matagne; Siddharth Rao; Subhali Subhechha; Lynn Verschueren; Mohammed Aftab Baig; Marie Garcia Bardon; Geert Hellings (CoRR, 2025)