Fault modelling and fault equivalence in CMOS technology. - Marie-Lise Flottes; Christian Landrault; Serge Pravossoudovitch (EURO-DAC, 1990)

Fault modeling and fault equivalence in CMOS technology. - Marie-Lise Flottes; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 1991)

A New Reliable Method for Delay-Fault Diagnosis. - Marie-Lise Flottes; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VLSI Design, 1992)

Automatic Synthesis of BISTed Data Paths From High Level Specification. - Marie-Lise Flottes; D. Hammad; Bruno Rouzeyre (EDAC-ETC-EUROASIC, 1994)

High-level synthesis for easy testability. - Marie-Lise Flottes; D. Hammad; Bruno Rouzeyre (ED&TC, 1995)

Is High-Level Test Synthesis Just Design for Test? - Christian Landrault; Marie-Lise Flottes; Bruno Rouzeyre (ITC, 1995)

Analyzing testability from behavioral to RT level. - Marie-Lise Flottes; R. Pires; Bruno Rouzeyre (ED&TC, 1997)

Improving Testability of Non-Scan Designs during Behavioral Synthesis. - Marie-Lise Flottes; D. Hammad; Bruno Rouzeyre (J. Electron. Test., 1997)

Alleviating DFT Cost Using Testability Driven HLS. - Marie-Lise Flottes; R. Pires; Bruno Rouzeyre (Asian Test Symposium, 1998)

Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. - Marie-Lise Flottes; R. Pires; Bruno Rouzeyre; Laurent Volpe (DATE, 1998)

Low Cost Partial Scan Design: A High Level Synthesis Approach. - Marie-Lise Flottes; R. Pires; Bruno Rouzeyre; Laurent Volpe (VTS, 1998)

Partial set for flip-flops based on state requirement for non-scan BIST scheme. - Marie-Lise Flottes; Christian Landrault; A. Petitqueux (ETW, 1999)

A Successful Distance-Learning Experience for IC Test Education. - Yves Bertrand; Florence Azaïs; Marie-Lise Flottes; Regis Lorival (MSE, 1999)

BISTing Datapaths under Heterogeneous Test Schemes. - David Berthelot; Marie-Lise Flottes; Bruno Rouzeyre (J. Electron. Test., 1999)

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. - Marie-Lise Flottes; Christian Landrault; A. Petitqueux (Asian Test Symposium, 2000)

A controller resynthesis based method for improving datapath testability. - Marie-Lise Flottes; Bruno Rouzeyre; Laurent Volpe (ISCAS, 2000)

BISTing data paths at behavioral level. - David Berthelot; Marie-Lise Flottes; Bruno Rouzeyre (ITC, 2000)

Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. - Marie-Lise Flottes; Julien Pouget; Bruno Rouzeyre (VLSI-SOC, 2001)

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. - David Berthelot; Marie-Lise Flottes; Bruno Rouzeyre (J. Electron. Test., 2001)

A Heuristic for Test Scheduling at System Level. - Marie-Lise Flottes; Julien Pouget; Bruno Rouzeyre (DATE, 2002)

European Network for Test Education. - Yves Bertrand; Marie-Lise Flottes; Florence Azaïs; Serge Bernard; Laurent Latorre; Regis Lorival (DELTA, 2002)

A simple and effective compression scheme for test pins reduction. - Marie-Lise Flottes; Regis Poirier; Bruno Rouzeyre (HLDVT, 2002)

Improving Datapath Testability by Modifying Controller Specification. - Marie-Lise Flottes; Bruno Rouzeyre; Laurent Volpe (VLSI Design, 2002)

An efficient approach to SoC wrapper design, TAM configuration and test scheduling. - Julien Pouget; Erik Larsson; Zebo Peng; Marie-Lise Flottes; Bruno Rouzeyre (ETW, 2003)

Test Engineering Education in Europe: the EuNICE-Test Project. - Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Anton Biasizzo; Franc Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich; Jean-Pierre Van der Heyden (MSE, 2003)

A Unified DFT Approach for BIST and External Test. - Marie-Lise Flottes; Christian Landrault; A. Petitqueux (J. Electron. Test., 2003)

An Arithmetic Structure for Test Data Horizontal Compression. - Marie-Lise Flottes; Regis Poirier; Bruno Rouzeyre (DATE, 2004)

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. - Marie-Lise Flottes; Yves Bertrand; Luz Balado; Emili Lupon; Anton Biasizzo; Franc Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich (DELTA, 2004)

On Using Test Vector Differences for Reducing Test Pin Numbers. - Marie-Lise Flottes; Regis Poirier; Bruno Rouzeyre (DELTA, 2004)

User-constrained test architecture design for modular SOC testing. - Ludovic A. Krundel; Sandeep Kumar Goel; Erik Jan Marinissen; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2004)

Scan Design and Secure Chip. - David Hély; Marie-Lise Flottes; Frédéric Bancel; Bruno Rouzeyre; Nicolas Bérard; Michel Renovell (IOLTS, 2004)

Mutation Sampling Technique for the Generation of Structural Test Data. - Mathieu Scholivé; Vincent Beroulle; Chantal Robach; Marie-Lise Flottes; Bruno Rouzeyre (DATE, 2005)

Test control for secure scan designs. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2005)

Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project. - Laurent Latorre; Yves Bertrand; Michel Robert; Marie-Lise Flottes (EDUTECH, 2005)

A secure scan design methodology. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (DATE, 2006)

Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. - Julien Dalmasso; Marie-Lise Flottes; Bruno Rouzeyre (DELTA, 2006)

Secure Scan Techniques: A Comparison. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2006)

Scan Pattern Watermarking. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (LATW, 2006)

A Novel Parity Bit Scheme for SBox in AES Circuits. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (DDECS, 2007)

An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2007)

A Dependable Parallel Architecture for SBoxes. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (ReCoSoC, 2007)

Test data compression and TAM design. - Julien Dalmasso; Marie-Lise Flottes; Bruno Rouzeyre (VLSI-SoC, 2007)

Compression-based SoC Test Infrastructures. - Julien Dalmasso; Marie-Lise Flottes; Bruno Rouzeyre (VLSI-SoC (Selected Papers), 2007)

Securing Scan Control in Crypto Chips. - David Hély; Frédéric Bancel; Marie-Lise Flottes; Bruno Rouzeyre (J. Electron. Test., 2007)

AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. - M. Doulcier; Marie-Lise Flottes; Bruno Rouzeyre (DELTA, 2008)

An Integrated Validation Environment for Differential Power Analysis. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (DELTA, 2008)

A Reliable Architecture for the Advanced Encryption Standard. - Giorgio Di Natale; M. Doulcier; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2008)

Improving the Test of NoC-Based SoCs with Help of Compression Schemes. - Julien Dalmasso; Érika F. Cota; Marie-Lise Flottes; Bruno Rouzeyre (ISVLSI, 2008)

Wireless Test Structure for Integrated Systems. - Ziad Noun; Philippe Cauvet; Marie-Lise Flottes; David Andreu 001; Serge Bernard (ITC, 2008)

Execution time reduction of Differential Power Analysis experiments. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (LATW, 2009)

A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. - Giorgio Di Natale; M. Doulcier; Marie-Lise Flottes; Bruno Rouzeyre (J. Electron. Test., 2009)

Remote Labs for Industrial IC Testing. - Beatrice Pradarelli; Laurent Latorre; Marie-Lise Flottes; Yves Bertrand; Pascal Nouet (IEEE Trans. Learn. Technol., 2009)

Ensuring high testability without degrading security: Embedded tutorial on "test and security". - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (DDECS, 2010)

Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (DELTA, 2010)

Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. - Kaouthar Bousselam; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2010)

Self-Test Techniques for Crypto-Devices. - Giorgio Di Natale; M. Doulcier; Marie-Lise Flottes; Bruno Rouzeyre (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Power consumption traces realignment to improve differential power analysis. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Miroslav Valka; Denis Réal (DDECS, 2011)

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. - Rodrigo Possamai Bastos; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (DFT, 2011)

Scan Attacks and Countermeasures in Presence of Scan Response Compactors. - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2011)

New security threats against chips containing scan chain structures. - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (HOST, 2011)

Timing issues for an efficient use of concurrent error detection codes. - Rodrigo Possamai Bastos; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (LATW, 2011)

A New Scan Attack on RSA in Presence of Industrial Countermeasures. - Jean DaRolt; Amitabh Das; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (COSADE, 2012)

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. - Jean DaRolt; Amitabh Das; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (DFT, 2012)

On-chip test comparison for protecting confidential data in secure ICs. - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2012)

Are advanced DfT structures sufficient for preventing scan-attacks? - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (VTS, 2012)

Scan attacks on side-channel and fault attack resistant public-key implementations. - Jean DaRolt; Amitabh Das; Santosh Ghosh; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (J. Cryptogr. Eng., 2012)

Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. - Rodrigo Possamai Bastos; Frank Sill Torres; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (Microelectron. Reliab., 2012)

On Countermeasures Against Fault Attacks on the Advanced Encryption Standard. - Kaouthar Bousselam; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (Fault Analysis in Cryptography, 2012)

Laser-Induced Fault Simulation. - Feng Lu; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (DSD, 2013)

A bulk built-in sensor for detection of fault attacks. - Rodrigo Possamai Bastos; Frank Sill Torres; Jean-Max Dutertre; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (HOST, 2013)

A BIST method for TSVs pre-bond test. - Hakim Zimouche; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IDT, 2013)

A smart test controller for scan chains in secure circuits. - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2013)

A 3D IC BIST for pre-bond test of TSVs using ring oscillators. - Yassine Fkih; Pascal Vivet; Bruno Rouzeyre; Marie-Lise Flottes; Giorgio Di Natale (NEWCAS, 2013)

A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. - Rodrigo Possamai Bastos; Frank Sill Torres; Jean-Max Dutertre; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (PATMOS, 2013)

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. - Rodrigo Possamai Bastos; Giorgio Di Natale; Marie-Lise Flottes; Feng Lu; Bruno Rouzeyre (J. Electron. Test., 2013)

Secure JTAG Implementation Using Schnorr Protocol. - Amitabh Das; Jean DaRolt; Santosh Ghosh; Stefaan Seys; Sophie Dupuis; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (J. Electron. Test., 2013)

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. - Sophie Dupuis; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (Inf. Secur. J. A Glob. Perspect., 2013)

Multilevel Ionizing-Induced Transient Fault Simulator. - Feng Lu; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (Inf. Secur. J. A Glob. Perspect., 2013)

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. - Jean-Max Dutertre; Rodrigo Possamai Bastos; Olivier Potin; Marie-Lise Flottes; Bruno Rouzeyre; Giorgio Di Natale (Microelectron. Reliab., 2013)

A novel differential scan attack on advanced DFT structures. - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (ACM Trans. Design Autom. Electr. Syst., 2013)

Laser attacks on integrated circuits: From CMOS to FD-SOI. - Jean-Max Dutertre; Stephan De Castro; Alexandre Sarafianos; Noemie Boher; Bruno Rouzeyre; Mathieu Lisart; Joel Damiens; Philippe Candelier; Marie-Lise Flottes; Giorgio Di Natale (DTIS, 2014)

Layout-aware laser fault injection simulation and modeling: From physical level to gate level. - Feng Lu; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Guillaume Hubert (DTIS, 2014)

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. - Sophie Dupuis; Papa-Sidi Ba; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2014)

Customized cell detector for laser-induced-fault detection. - Feng Lu; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IOLTS, 2014)

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. - Yassine Fkih; Pascal Vivet; Bruno Rouzeyre; Marie-Lise Flottes; Giorgio Di Natale; Juergen Schloeffel (ISVLSI, 2014)

Laser-Induced Fault Effects in Security-Dedicated Circuits. - Vincent Beroulle; Philippe Candelier; Stephan De Castro; Giorgio Di Natale; Jean-Max Dutertre; Marie-Lise Flottes; David Hély; Guillaume Hubert; Régis Leveugle; Feng Lu; Paolo Maistri; Athanasios Papadimitriou; et al. (VLSI-SoC (Selected Papers), 2014)

Laser-induced fault effects in security-dedicated circuits. - Régis Leveugle; Paolo Maistri; Pierre Vanhauwaert; Feng Lu; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Athanasios Papadimitriou; David Hély; Vincent Beroulle; Guillaume Hubert; Stephan De Castro; et al. (VLSI-SoC, 2014)

Built-in self-test for manufacturing TSV defects before bonding. - Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Hakim Zimouche (VTS, 2014)

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. - Jean-Max Dutertre; Rodrigo Possamai Bastos; Olivier Potin; Marie-Lise Flottes; Bruno Rouzeyre; Giorgio Di Natale; Alexandre Sarafianos (Microelectron. Reliab., 2014)

Test Versus Security: Past and Present. - Jean DaRolt; Amitabh Das; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (IEEE Trans. Emerg. Top. Comput., 2014)

Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. - Jean DaRolt; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IEEE Trans. Very Large Scale Integr. Syst., 2014)

New testing procedure for finding insertion sites of stealthy hardware trojans. - Sophie Dupuis; Papa-Sidi Ba; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (DATE, 2015)

On the limitations of logic testing for detecting Hardware Trojans Horses. - Marie-Lise Flottes; Sophie Dupuis; Papa-Sidi Ba; Bruno Rouzeyre (DTIS, 2015)

Hardware Trojan prevention using layout-level design approach. - Papa-Sidi Ba; Palanichamy Manikandan; Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (ECCTD, 2015)

Session-less based thermal-aware 3D-SIC test scheduling. - Marie-Lise Flottes; Joao Azevedo; Giorgio Di Natale; Bruno Rouzeyre (ETS, 2015)

Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. - Stephan De Castro; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Jean-Max Dutertre (ISVLSI, 2015)

3D DFT Challenges and Solutions. - Yassine Fkih; Pascal Vivet; Marie-Lise Flottes; Bruno Rouzeyre; Giorgio Di Natale; Juergen Schloeffel (ISVLSI, 2015)

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. - Papa-Sidi Ba; Sophie Dupuis; Palanichamy Manikandan; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (ISVLSI, 2016)

Using outliers to detect stealthy hardware trojan triggering? - Papa-Sidy Ba; Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (IVSW, 2016)

Frontside Versus Backside Laser Injection: A Comparative Study. - Stephan De Castro; Jean-Max Dutertre; Bruno Rouzeyre; Giorgio Di Natale; Marie-Lise Flottes (ACM J. Emerg. Technol. Comput. Syst., 2016)

Scan chain encryption for the test, diagnosis and debug of secure circuits. - Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre; Paolo Prinetto; Marco Restifo (ETS, 2017)

Hacking the Control Flow error detection mechanism. - Giorgio Di Natale; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (IVSW, 2017)

Experimentations on scan chain encryption with PRESENT. - Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (IVSW, 2017)

SI ECCS: SECure context saving for IoT devices. - Emanuele Valea; Mathieu Da Silva; Giorgio Di Natale; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (DTIS, 2018)

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. - Jean-Max Dutertre; Vincent Beroulle; Philippe Candelier; Stephan De Castro; Louis-Barthelemy Faber; Marie-Lise Flottes; Philippe Gendrier; David Hély; Régis Leveugle; Paolo Maistri; Giorgio Di Natale; Athanasios Papadimitriou; et al. (FDTC, 2018)

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. - Jean-Max Dutertre; Vincent Beroulle; Philippe Candelier; Louis-Barthelemy Faber; Marie-Lise Flottes; Philippe Gendrier; David Hély; Régis Leveugle; Paolo Maistri; Giorgio Di Natale; Athanasios Papadimitriou; Bruno Rouzeyre (IOLTS, 2018)

A New Secure Stream Cipher for Scan Chain Encryption. - Mathieu Da Silva; Emanuele Valea; Marie-Lise Flottes; Sophie Dupuis; Giorgio Di Natale; Bruno Rouzeyre (IVSW, 2018)

Encryption of test data: which cipher is better? - Mathieu Da Silva; Emanuele Valea; Marie-Lise Flottes; Sophie Dupuis; Giorgio Di Natale; Bruno Rouzeyre (PRIME, 2018)

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. - Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (IEEE Des. Test, 2018)

Assessing body built-in current sensors for detection of multiple transient faults. - Raphael Andreoni Camponogara Viera; Jean-Max Dutertre; Marie-Lise Flottes; Olivier Potin; Giorgio Di Natale; Bruno Rouzeyre; Rodrigo Possamai Bastos (Microelectron. Reliab., 2018)

Encryption-Based Secure JTAG. - Emanuele Valea; Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (DDECS, 2019)

Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. - Emanuele Valea; Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Sophie Dupuis; Bruno Rouzeyre (DTIS, 2019)

A Comprehensive Approach to a Trusted Test Infrastructure. - Marc Merandat; Vincent Reynaud; Emanuele Valea; Jérôme Quévremont; Nicolas Valette; Paolo Maistri; Régis Leveugle; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre; Giorgio Di Natale (IVSW, 2019)

SECCS: SECure Context Saving for IoT Devices. - Emanuele Valea; Mathieu Da Silva; Giorgio Di Natale; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (CoRR, 2019)

A Survey on Security Threats and Countermeasures in IEEE Test Standards. - Emanuele Valea; Mathieu Da Silva; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre (IEEE Des. Test, 2019)

Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. - Sophie Dupuis; Marie-Lise Flottes (J. Electron. Test., 2019)

Stream vs block ciphers for scan encryption. - Emanuele Valea; Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (Microelectron. J., 2019)

Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. - Mathieu Da Silva; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. - Florence Azaïs; Serge Bernard; Mariane Comte; Bastien Deveautour; Sophie Dupuis; Hassan El Badawi; Marie-Lise Flottes; Patrick Girard 001; Vincent Kerzèrho; Laurent Latorre; François Lefèvre; Bruno Rouzeyre; et al. (IOLTS, 2020)

A Secure Scan Controller for Protecting Logic Locking. - Quang-Linh Nguyen; Emanuele Valea; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (IOLTS, 2020)

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. - Lila Ammoura; Marie-Lise Flottes; Patrick Girard 001; Arnaud Virazel (DTIS, 2021)

A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. - S. Lapeyre; Nicolas Valette; Marc Merandat; Marie-Lise Flottes; Bruno Rouzeyre; Arnaud Virazel (ETS, 2021)

High-level Intellectual Property Obfuscation via Decoy Constants. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IOLTS, 2021)

On Preventing SAT Attack with Decoy Key-Inputs. - Quang-Linh Nguyen; Marie-Lise Flottes; Sophie Dupuis; Bruno Rouzeyre (ISVLSI, 2021)

Leveraging Layout-based Effects for Locking Analog ICs. - Muayad J. Aljafar; Florence Azaïs; Marie-Lise Flottes; Samuel Pagliarini (ASHES@CCS, 2022)

A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. - S. Lapeyre; Nicolas Valette; Marc Merandat; Marie-Lise Flottes; Bruno Rouzeyre; Arnaud Virazel (ETS, 2022)

Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. - Lila Ammoura; Marie-Lise Flottes; Patrick Girard 001; Jean-Philippe Noel; Arnaud Virazel (ETS, 2023)

Resynthesis-based Attacks Against Logic Locking. - Felipe Almeida; Levent Aksoy; Quang-Linh Nguyen; Sophie Dupuis; Marie-Lise Flottes; Samuel Pagliarini (ISQED, 2023)

Hybrid Protection of Digital FIR Filters. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. - Lila Ammoura; Marie-Lise Flottes; Patrick Girard 001; Jean-Philippe Noel; Arnaud Virazel (DATE, 2024)

Power Analysis Attack Against post-SAT Logic Locking schemes. - Nassim Riadi; Florent Bruguier; Pascal Benoit; Sophie Dupuis; Marie-Lise Flottes (ETS, 2024)

Logic Locking: Exploration of a new key-gate based on tristate logic. - Sophie Dupuis; Nassim Riadi; Clémy Moroukian; Florence Azaïs; Marie-Lise Flottes (LATS, 2024)

Utilizing layout effects for analog logic locking. - Muayad J. Aljafar; Florence Azaïs; Marie-Lise Flottes; Samuel Pagliarini (J. Cryptogr. Eng., 2024)