A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. - Sebastian Höppner; Chenming Shao; Holger Eisenreich; Georg Ellguth; Mario Ander; René Schüffny (ISCAS, 2012)

A 32 GBit/s communication SoC for a waferscale neuromorphic system. - Stefan Scholze; Holger Eisenreich; Sebastian Höppner; Georg Ellguth; Stephan Henker; Mario Ander; Stefan Hänzsche; Johannes Partzsch; Christian Mayr 001; René Schüffny (Integr., 2012)