A Systolic Algorithm and Architecture for Galois Field Arithmetic. - Mario Kovac; N. Ranganathan; M. Varanasi (IPPS, 1992)

SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. - Mario Kovac; N. Ranganathan; M. Varanasi (VLSI Design, 1993)

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. - Mario Kovac; N. Ranganathan; M. Varanasi (IEEE Trans. Very Large Scale Integr. Syst., 1993)

ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. - Mario Kovac; N. Ranganathan (VLSI Design, 1994)

A prototype VLSI chip architecture for JPEG image compression. - Mario Kovac; N. Ranganathan; Martin Zagar (ED&TC, 1995)

JAGUAR: a high speed VLSI chip for JPEG image compression standard. - Mario Kovac; N. Ranganathan (VLSI Design, 1995)

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. - Mario Kovac; N. Ranganathan (Proc. IEEE, 1995)

Universal Strong Encryption FPGA Core Implementation. - Davor Runje; Mario Kovac (DATE, 1998)

Application of Dynamically Reconfigurable Processors in Digital Signal Processing. - Hrvoje Mlinaric; Mario Kovac; Josip Knezovic (SIGMAP, 2006)

Power consumption and bandwidth savings with video transcoding to mobile device-specific spatial resolution. - Leon Dragic; Daniel Hofman; Mario Kovac; Martin Zagar; Josip Knezovic (CSNDSP, 2014)

Unified, multiple target, computer engineering learning platform. - Martin Zagar; Nikolina Frid; Josip Knezovic; Daniel Hofman; Mario Kovac; Vlado Sruk; Hrvoje Mlinaric (EDUCON, 2014)

Computer Engineering Laboratory Course: E2LP Platform Experience. - Nikolina Frid; Vlado Sruk; Hrvoje Mlinaric; Mario Kovac (E2LP@FedCSIS, 2014)

E-Health Demystified: An E-Government Showcase. - Mario Kovac (Computer, 2014)

The MANGO FET-HPC Project: An Overview. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Alessandro Cilardo; William Fornaciari; Mario Kovac; Fabrice Roudet; Davide Zoni (CSE, 2015)

Work in progress: Embedded computer engineering learning platform capabilities. - Martin Zagar; Nikolina Frid; Josip Knezovic; Daniel Hofman; Mario Kovac; Vlado Sruk; Hrvoje Mlinaric (EDUCON, 2015)

Enabling HPC for QoS-sensitive applications: The MANGO approach. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Carlo Brandolese; Alessandro Cilardo; William Fornaciari; Ynse Hoornenborg; Mario Kovac; Bruno Maitre; Giuseppe Massari; Hrvoje Mlinaric; et al. (DATE, 2016)

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Carlo Brandolese; Etienne Cappe; Alessandro Cilardo; Leon Dragic; Alexandre Dray; Alen Duspara; William Fornaciari; Gerald Guillaume; et al. (DSD, 2017)

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. - José Flich; Alessandro Cilardo; Mario Kovaç; Rafael Tornero; Mirko Gagliardi; Edoardo Fusella; José Maria Martínez; Tomás Picornell (PARCO, 2017)

Thermal characterization of next-generation workloads on heterogeneous MPSoCs. - Arman Iranfar; Federico Terraneo; William Andrew Simon; Leon Dragic; Igor Piljic; Marina Zapater; William Fornaciari; Mario Kovac; David Atienza (SAMOS, 2017)

Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation. - Arman Iranfar; Ali Pahlevan; Marina Zapater; Martin Zagar; Mario Kovac; David Atienza (DATE, 2018)

Exploring manycore architectures for next-generation HPC systems through the MANGO approach. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Carlo Brandolese; Etienne Cappe; Alessandro Cilardo; Leon Dragic; Alexandre Dray; Alen Duspara; William Fornaciari; Edoardo Fusella; et al. (Microprocess. Microsystems, 2018)

European processor initiative: the industrial cornerstone of EuroHPC for exascale era. - Mario Kovac (CF, 2019)

Bolt65 - performance-optimized HEVC HW/SW suite for Just-in-Time video processing. - Igor Piljic; Leon Dragic; Alen Duspara; Mate Cobrnic; Hrvoje Mlinaric; Mario Kovac (MIPRO, 2019)

An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator. - Mate Cobrnic; Alen Duspara; Leon Dragic; Igor Piljic; Hrvoje Mlinaric; Mario Kovac (PPAM (1), 2019)

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit. - Mate Kovac; Leon Dragic; Branimir Malnar; Francesco Minervini; Oscar Palomar; Carlos Rojas; Mauro Olivieri; Josip Knezovic; Mario Kovac (Microprocess. Microsystems, 2023)

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. - Francesco Minervini; Oscar Palomar; Osman S. Unsal; Enrico Reggiani; Josue V. Quiroga; Joan Marimon; Carlos Rojas; Roger Figueras; Abraham Ruiz; Alberto González 004; Jonnatan Mendoza; Iván Vargas; et al. (ACM Trans. Archit. Code Optim., 2023)

High-Performance Computing Storage Performance and Design Patterns - Btrfs and ZFS Performance for Different Use Cases. - Vedran Dakic; Mario Kovac; Igor Videc (Comput., 2024)