System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. - Mário P. Véstias; Horácio C. Neto (IEEE International Workshop on Rapid System Prototyping, 2002)

DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. - Mário P. Véstias; Horácio C. Neto (SBCCI, 2003)

Area/Performance Improvement of NoC Architectures. - Mário P. Véstias; Horácio C. Neto (ARC, 2006)

Co-synthesis of a configurable SoC platform based on a network on chip architecture. - Mário P. Véstias; Horácio C. Neto (ASP-DAC, 2006)

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. - Mário P. Véstias; Horácio C. Neto (FPL, 2006)

Area and performance optimization of a generic network-on-chip architecture. - Mário P. Véstias; Horácio C. Neto (SBCCI, 2006)

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. - Mário P. Véstias; Horácio C. Neto (FPL, 2007)

Multiplier-based double precision floating point divider according to the IEEE-754 standard. - Vítor Silva; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto (ARC, 2008)

Decimal multiplier on FPGA using embedded binary multipliers. - Horácio C. Neto; Mário P. Véstias (FPL, 2008)

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. - Rui Policarpo Duarte; Horácio C. Neto; Mário P. Véstias (DSD, 2009)

Run-Time Reconfigurable Array Using Magnetic RAM. - Victor Silva 001; Luís Bica Oliveira; Jorge R. Fernandes; Mário P. Véstias; Horácio C. Neto (DSD, 2009)

Revisiting the Newton-Raphson Iterative Method for Decimal Division. - Mário P. Véstias; Horácio C. Neto (FPL, 2011)

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. - Mário P. Véstias; Horácio C. Neto (DSD, 2012)

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. - Mário P. Véstias; Horácio C. Neto; Helena Sarmento (DSD, 2012)

Sliding block Viterbi decoders in FPGA. - Mário P. Véstias; Horácio C. Neto; Helena Sarmento (FPL, 2012)

Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA. - Mário P. Véstias (ICCE-Berlin, 2012)

Design of an IEEE 802.15.3c baseband processor in FPGA. - Mário P. Véstias; Helena Sarmento (ICCE-Berlin, 2012)

Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems. - Mário P. Véstias; Helena Sarmento (ICCE-Berlin, 2012)

Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. - Victor Silva 001; Mário P. Véstias; Horácio C. Neto; Jorge R. Fernandes (ICECS, 2012)

A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. - Victor Silva 001; Jorge R. Fernandes; Mário P. Véstias; Horácio C. Neto (ReConFig, 2012)

Analysis of matrix multiplication on high density Virtex-7 FPGA. - Wilson José; Ana Rita Silva; Horácio C. Neto; Mário P. Véstias (FPL, 2013)

A reconfigurable computing architecture using magnetic tunneling junction memories. - Victor Silva 001; Jorge R. Fernandes; Mário P. Véstias; Horácio C. Neto (FPL, 2013)

Design of a massively parallel computing architecture for dense matrix multiplication. - Wilson José; Ana Rita Silva; Mário P. Véstias; Horácio C. Neto (LASCAS, 2013)

Design of a multiband full-rate ultra-wideband receiver in FPGA. - Mário P. Véstias; Horácio C. Neto; Helena Sarmento (LASCAS, 2013)

Very low resource table-based FPGA evaluation of elementary functions. - Horácio C. Neto; Mário P. Véstias (ReConFig, 2013)

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. - Wilson José; Ana Rita Silva; Horácio C. Neto; Mário P. Véstias (FPL, 2014)

Trends of CPU, GPU and FPGA for high-performance computing. - Mário P. Véstias; Horácio C. Neto (FPL, 2014)

A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. - Mário P. Véstias; Horácio C. Neto (CoRR, 2014)

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. - João Pinhão; Wilson José; Horácio C. Neto; Mário P. Véstias (DSD, 2015)

Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA. - Tiago Rodrigues; Mário P. Véstias (DSD, 2015)

Enhancing stochastic computations via process variation. - Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto (FPL, 2015)

FPGA-based architecture for hyperspectral unmixing. - José M. P. Nascimento; Mário P. Véstias; Gabriel Martín (IGARSS, 2015)

Designing Hardware/Software Systems for Embedded High-Performance Computing. - Mário P. Véstias; Rui Policarpo Duarte; Horácio C. Neto (CoRR, 2015)

Multi-core for K-means clustering on FPGA. - Jose Canilho; Mário P. Véstias; Horácio C. Neto (FPL, 2016)

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. - Rui Policarpo Duarte; Horácio C. Neto; Mário P. Véstias (ICRC, 2016)

K-means clustering on CGRA. - João D. Lopes; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (FPL, 2017)

Parallel dot-products for deep learning on FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2017)

Decimal addition on FPGA based on a mixed BCD/excess-6 representation. - Horácio C. Neto; Mário P. Véstias (Microprocess. Microsystems, 2017)

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2018)

Improving the area of fast parallel decimal multipliers. - Mário P. Véstias; Horácio C. Neto (Microprocess. Microsystems, 2018)

Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs. - Ana Gonçalves; Tiago Peres; Mário P. Véstias (ARC, 2019)

Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning. - Tiago Peres; Ana Gonçalves; Mário P. Véstias (ARC, 2019)

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2019)

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. - Luís Fiolhais; Fernando M. Gonçalves; Rui Policarpo Duarte; Mário P. Véstias; José T. de Sousa (ISCAS, 2019)

A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing. - Mário P. Véstias (Algorithms, 2019)

Processing Systems for Deep Learning Inference on Edge Devices. - Mário P. Véstias (Convergence of Artificial Intelligence and the Internet of Things, 2020)

Implementing CNNs Using a Linear Array of Full Mesh CGRAs. - Valter Mário; João D. Lopes; Mário P. Véstias; José T. de Sousa (ARC, 2020)

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (IEEE Access, 2020)

Moving Deep Learning to the Edge. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Algorithms, 2020)

A fast and scalable architecture to run convolutional neural networks in low density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Microprocess. Microsystems, 2020)

Hyperspectral Compressive Sensing With a System-On-Chip FPGA. - José M. P. Nascimento; Mário P. Véstias; Gabriel Martín (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2020)

A Full Featured Configurable Accelerator for Object Detection With YOLO. - Daniel Pestana; Pedro R. Miranda; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (IEEE Access, 2021)

IOb-Cache: A High-Performance Configurable Open-Source Cache. - João V. Roque; João D. Lopes; Mário P. Véstias; José T. de Sousa (Algorithms, 2021)

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. - Mário P. Véstias; Horácio C. Neto (Algorithms, 2021)

Configurable Hardware Core for IoT Object Detection. - Pedro R. Miranda; Daniel Pestana; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (Future Internet, 2021)

Efficient Design of Pruned Convolutional Neural Networks on FPGA. - Mário P. Véstias (J. Signal Process. Syst., 2021)

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. - Helena Cruz; Mário P. Véstias; José Monteiro 001; Horácio C. Neto; Rui Policarpo Duarte (Remote. Sens., 2022)

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. - David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022)

Smart Embedded System for Skin Cancer Classification. - Pedro F. Durães; Mário P. Véstias (Future Internet, 2023)

Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. - Maria Inês Frutuoso; Horácio C. Neto; Mário P. Véstias; Rui Policarpo Duarte (Algorithms, 2023)

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (ACM Trans. Reconfigurable Technol. Syst., 2023)

LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. - Henrique B. Brum; Mário P. Véstias; Horácio C. Neto (ARC, 2024)

PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. - José T. de Sousa; João D. Lopes; Micaela Serôdio; Horácio C. Neto; Mário P. Véstias (ARITH, 2024)

Enhancing Urban Intersection Efficiency: Visible Light Communication and Learning-Based Control for Traffic Signal Optimization and Vehicle Management. - Manuel Augusto M. Vieira; Gonçalo Galvão; Manuela Vieira; Paula Louro; Mário P. Véstias; Pedro Vieira 001 (Symmetry, 2024)

Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. - Miguel Reis; Mário P. Véstias; Horácio C. Neto (ACM Trans. Reconfigurable Technol. Syst., 2024)