HiBRIC-MEM, a Memory Controller for PowerPC Based Systems. - Mario Porrmann; Ulrich Rückert 001; Karl Michael Marks; Jörg Landmann (EUROMICRO, 1997)

A High Performance SOFM Hardware-System. - Stefan Rüping 002; Mario Porrmann; Ulrich Rückert 001 (IWANN, 1997)

SOM accelerator system. - Stefan Rüping 002; Mario Porrmann; Ulrich Rückert 001 (Neurocomputing, 1998)

Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics. - Heiko Kalte; Mario Porrmann; Ulrich Rückert 001 (PDPTA, 2000)

A reconfigurable SOM hardware accelerator. - Mario Porrmann; Marc Franzmeier; Heiko Kalte; Ulf Witkowski; Ulrich Rückert 001 (ESANN, 2002)

Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations. - Mario Porrmann; Ulf Witkowski; Heiko Kalte; Ulrich Rückert 001 (FPL, 2002)

Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. - Mario Porrmann; Ulf Witkowski; Heiko Kalte; Ulrich Rückert 001 (PDP, 2002)

Leistungsbewertung eingebetteter Neurocomputersysteme. - Mario Porrmann (2002)

A holistic methodology for network processor design. - Olaf Bonorden; Nikolaus Brüls; Uwe Kastens; Dinh Khoi Le; Friedhelm Meyer auf der Heide; Jörg-Christian Niemann; Mario Porrmann; Ulrich Rückert 001; Adrian Slowik; Michael Thies (LCN, 2003)

A massively parallel architecture for self-organizing feature maps. - Mario Porrmann; Ulf Witkowski; Ulrich Rückert 001 (IEEE Trans. Neural Networks, 2003)

Leistungsbewertung unterschiedlicher Einbettungsvariaten dynamisch rekonfigurierbarer Hardware. - Heiko Kalte; Mario Porrmann; Ulrich Rückert 001 (ARCS Workshops, 2004)

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC. - Matthias Grünewald; Jörg-Christian Niemann; Mario Porrmann; Ulrich Rückert 001 (DATE, 2004)

A Comparative Study on System Approaches for Partially Reconfigurable Architectures. - Heiko Kalte; Markus Koester; Boris Kettelhoit; Mario Porrmann; Ulrich Rückert 001 (ERSA, 2004)

Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. - Björn Griese; Erik Vonnahme; Mario Porrmann; Ulrich Rückert 001 (FPL, 2004)

Study on column wise design compaction for reconfigurable systems. - Heiko Kalte; Gareth Lee; Mario Porrmann; Ulrich Rückert 001 (FPT, 2004)

gNBX - reconfigurable hardware acceleration of self-organizing maps. - Christopher Pohl; Marc Franzmeier; Mario Porrmann; Ulrich Rückert 001 (FPT, 2004)

System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement. - Heiko Kalte; Mario Porrmann; Ulrich Rückert 001 (IPDPS, 2004)

Hardware Accelerated Data Analysis. - Marc Franzmeier; Christopher Pohl; Mario Porrmann; Ulrich Rückert 001 (PARELEC, 2004)

Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. - Matthias Grünewald; Dinh Khoi Le; Uwe Kastens; Jörg-Christian Niemann; Mario Porrmann; Ulrich Rückert 001; Adrian Slowik; Michael Thies (PARELEC, 2004)

Dynamic Reconfiguration of Real-Time Network Interfaces. - Erik Vonnahme; Björn Griese; Mario Porrmann; Ulrich Rückert 001 (PARELEC, 2004)

Context Saving and Restoring for Multitasking in Reconfigurable Systems. - Heiko Kalte; Mario Porrmann (FPL, 2005)

Task Placement for Heterogeneous Reconfigurable Architectures. - Markus Koester; Mario Porrmann; Heiko Kalte (FPT, 2005)

Adaptable Switch Boxes as On-Chip Routing Nodes for Networks-on-Chip. - Ralf Eickhoff; Jörg-Christian Niemann; Mario Porrmann; Ulrich Rückert 001 (IESS, 2005)

Component Case Study of a Self-Optimizing RCOS/RTOS System. - Björn Griese; Simon Oberthür; Mario Porrmann (IESS, 2005)

REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. - Heiko Kalte; Gareth Lee; Mario Porrmann; Ulrich Rückert 001 (IPDPS, 2005)

Placement-Oriented Modeling of Partially Reconfigurable Architectures. - Markus Koester; Mario Porrmann; Ulrich Rückert 001 (IPDPS, 2005)

A Scalable Parallel SoC Architecture for Network Processors. - Jörg-Christian Niemann; Mario Porrmann; Ulrich Rückert 001 (ISVLSI, 2005)

Defragmentation Algorithms for Partially Reconfigurable Hardware. - Markus Koester; Heiko Kalte; Mario Porrmann; Ulrich Rückert 001 (VLSI-SoC, 2005)

A system approach for partially reconfigurable architectures. - Heiko Kalte; Boris Kettelhoit; Markus Köster; Mario Porrmann; Ulrich Rückert 001 (Int. J. Embed. Syst., 2005)

GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. - Jörg-Christian Niemann; Christoph Puttmann; Mario Porrmann; Ulrich Rückert 001 (ARCS, 2006)

REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs. - Heiko Kalte; Mario Porrmann (Conf. Computing Frontiers, 2006)

Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. - Markus Koester; Heiko Kalte; Mario Porrmann (ERSA, 2006)

A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. - Boris Kettelhoit; Mario Porrmann (FPL, 2006)

Reconfigurable hardware in-the-loop simulations for digital control design. - Carlos Paiz; Christopher Pohl; Mario Porrmann (ICINCO-SPSMC, 2006)

A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems. - Björn Griese; Mario Porrmann (BICC, 2006)

Dedicated module access in dynamically reconfigurable systems. - Jens Hagemeyer; Boris Kettelhoit; Mario Porrmann (IPDPS, 2006)

Bio-inspired massively parallel architectures for nanotechnologies. - Björn Jäger; Mario Porrmann; Ulrich Rückert 001 (ISCAS, 2006)

Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors. - Björn Griese; Boris Kettelhoit; Mario Porrmann (PARELEC, 2006)

Application-Driven Development of Concurrent Packet Processing Platforms. - Christian Sauer 001; Matthias Gries; Jörg-Christian Niemann; Mario Porrmann; Michael Thies (PARELEC, 2006)

A Multiprocessor Cache for Massively Parallel SoC Architectures. - Jörg-Christian Niemann; Christian Liß; Mario Porrmann; Ulrich Rückert 001 (ARCS, 2007)

GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. - Christoph Puttmann; Jörg-Christian Niemann; Mario Porrmann; Ulrich Rückert 001 (DSD, 2007)

Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. - Jens Hagemeyer; Boris Kettelhoit; Markus Koester; Mario Porrmann (ERSA, 2007)

A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs. - Jens Hagemeyer; Boris Kettelhoit; Markus Koester; Mario Porrmann (FPL, 2007)

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. - Vincenzo Rana; Marco D. Santambrogio; Donatella Sciuto; Boris Kettelhoit; Markus Köster; Mario Porrmann; Ulrich Rückert 001 (IPDPS, 2007)

A design framework for FPGA-based dynamically reconfigurable digital controllers. - Carlos Paiz; Boris Kettelhoit; Mario Porrmann (ISCAS, 2007)

Resource efficiency of the GigaNetIC chip multiprocessor architecture. - Jörg-Christian Niemann; Christoph Puttmann; Mario Porrmann; Ulrich Rückert 001 (J. Syst. Archit., 2007)

Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. - Madhura Purnaprajna; Christoph Puttmann; Mario Porrmann (DATE, 2008)

SelfS - A real-time protocol for virtual ring topologies. - Björn Griese; André Brinkmann; Mario Porrmann (IPDPS, 2008)

Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography. - Christoph Puttmann; Jamshid Shokrollahi; Mario Porrmann (ITNG, 2008)

Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance. - Mario Porrmann; Madhura Purnaprajna; Christoph Puttmann (AHS, 2009)

Design optimizations to improve placeability of partial reconfiguration modules. - Markus Koester; Wayne Luk; Jens Hagemeyer; Mario Porrmann (DATE, 2009)

SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. - Paolo Roberto Grassi; Marco D. Santambrogio; Jens Hagemeyer; Christopher Pohl; Mario Porrmann (ERSA, 2009)

Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. - Madhura Purnaprajna; Christopher Pohl; Mario Porrmann; Ulrich Rückert 001 (ERSA, 2009)

A Synchronization Method for Register Traces of Pipelined Processors. - Ralf Dreesen; Thorsten Jungeblut; Michael Thies; Mario Porrmann; Uwe Kastens; Ulrich Rückert 001 (IESS, 2009)

RAPTOR - A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. - Mario Porrmann; Jens Hagemeyer; Johannes Romoth; Manuel Strugholtz; Christopher Pohl (PARCO, 2009)

vMAGIC - Automatic Code Generation for VHDL. - Christopher Pohl; Carlos Paiz; Mario Porrmann (Int. J. Reconfigurable Comput., 2009)

Run-time reconfigurability in embedded multiprocessors. - Madhura Purnaprajna; Mario Porrmann; Ulrich Rückert 001 (SIGARCH Comput. Archit. News, 2009)

High level specification of embedded listeners for monitoring of Network-on-Chips. - Christoph Puttmann; Mario Porrmann; Paolo Roberto Grassi; Marco D. Santambrogio; Ulrich Rückert 001 (ISCAS, 2010)

A Framework for the Design Space Exploration of Software-Defined Radio Applications. - Thorsten Jungeblut; Ralf Dreesen; Mario Porrmann; Michael Thies; Ulrich Rückert 001; Uwe Kastens (MOBILIGHT, 2010)

Design Space Exploration for Memory Subsystems of VLIW Architectures. - Thorsten Jungeblut; Gregor Sievers; Mario Porrmann; Ulrich Rückert 001 (NAS, 2010)

Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. - Madhura Purnaprajna; Mario Porrmann; Ulrich Rückert 001; Michael Hussmann; Michael Thies; Uwe Kastens (ACM Trans. Reconfigurable Technol. Syst., 2010)

Analysis of SEU effects in partially reconfigurable SoPCs. - Luca Sterpone; Fabio Margaglia; Markus Köster; Jens Hagemeyer; Mario Porrmann (AHS, 2011)

Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. - Sebastian Korf; Dario Cozzi; Markus Koester; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001; Marco D. Santambrogio (FCCM, 2011)

Evaluation of Applied Intra-disk Redundancy Schemes to Improve Single Disk Reliability. - Matthias Grawinkel; Thorsten Schäfer; André Brinkmann; Jens Hagemeyer; Mario Porrmann (MASCOTS, 2011)

Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms. - Federico Nava; Donatella Sciuto; Marco D. Santambrogio; Stefan Herbrechtsmeier; Mario Porrmann; Ulf Witkowski; Ulrich Rückert 001 (ACM Trans. Reconfigurable Technol. Syst., 2011)

Design Optimizations for Tiled Partially Reconfigurable Systems. - Markus Koester; Wayne Luk; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A scalable platform for run-time reconfigurable satellite payload processing. - Jens Hagemeyer; Arne Hilgenstein; Dirk Jungewelter; Dario Cozzi; Carmelo Felicetti; Ulrich Rückert 001; Sebastian Korf; Markus Koester; Fabio Margaglia; Mario Porrmann; Florian Dittmann 001; Michael Ditze; et al. (AHS, 2012)

gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps. - Jan Lachmair; Erzsébet Merényi; Mario Porrmann; Ulrich Rückert 001 (ESANN, 2012)

Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling. - Gianluca Durelli; Federica Cresci; Donatella Sciuto; Mario Porrmann; Marco D. Santambrogio (IPDPS Workshops, 2012)

A TCMS-based architecture for GALS NoCs. - Thorsten Jungeblut; Johannes Ax; Mario Porrmann; Ulrich Rückert 001 (ISCAS, 2012)

A 200mV 32b subthreshold processor with adaptive supply voltage control. - Sven Lütkemeier; Thorsten Jungeblut; Mario Porrmann; Ulrich Rückert 001 (ISSCC, 2012)

Optimizing inter-FPGA communication by automatic channel adaptation. - Johannes Romoth; Dirk Jungewelter; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (ReConFig, 2012)

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. - Luca Sterpone; Davide Sabena; Anees Ullah; Mario Porrmann; Jens Hagemeyer; Jørgen Ilstad (AHS, 2013)

On-line testing of permanent radiation effects in reconfigurable systems. - Luca Cassano; Dario Cozzi; Sebastian Korf; Jens Hagemeyer; Mario Porrmann; Luca Sterpone (DATE, 2013)

Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications. - Gregor Sievers; Peter Christ; Julian Einhaus; Thorsten Jungeblut; Mario Porrmann; Ulrich Rückert 001 (NORCHIP, 2013)

A reconfigurable neuroprocessor for self-organizing feature maps. - Jan Lachmair; Erzsébet Merényi; Mario Porrmann; Ulrich Rückert 001 (Neurocomputing, 2013)

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. - Sven Lütkemeier; Thorsten Jungeblut; Hans Kristian Otnes Berge; Snorre Aunet; Mario Porrmann; Ulrich Rückert 001 (IEEE J. Solid State Circuits, 2013)

A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. - Luca Sterpone; Mario Porrmann; Jens Hagemeyer (IEEE Trans. Computers, 2013)

A systematic approach for optimized bypass configurations for application-specific embedded processors. - Thorsten Jungeblut; Boris Hübener; Mario Porrmann; Ulrich Rückert 001 (ACM Trans. Embed. Comput. Syst., 2013)

Methods for the Design and Development. - Harald Anacker; Michael Dellnitz; Kathrin Flaßkamp; Stefan Groesbrink; Philip Hartmann; Christian Heinzemann; Christian Horenkamp; Bernd Kleinjohann; Lisa Kleinjohann; Sebastian Korf; Martin Krüger; Wolfgang Müller 003; et al. (Design Methodology for Intelligent Technical Systems, 2014)

The Paradigm of Self-optimization. - Michael Dellnitz; Roman Dumitrescu; Kathrin Flaßkamp; Jürgen Gausemeier; Philip Hartmann; Peter Iwanek; Sebastian Korf; Martin Krüger; Sina Ober-Blöbaum; Mario Porrmann; Claudia Priesterjahn; Katharina Stahl; et al. (Design Methodology for Intelligent Technical Systems, 2014)

Development of Self-optimizing Systems. - Jürgen Gausemeier; Sebastian Korf; Mario Porrmann; Katharina Stahl; Oliver Sudmann; Mareen Vaßholz (Design Methodology for Intelligent Technical Systems, 2014)

Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems. - Domenico G. Sorrenti; Dario Cozzi; Sebastian Korf; Luca Cassano; Jens Hagemeyer; Mario Porrmann; Cinzia Bernardeschi (DFT, 2014)

An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems. - Luca Cassano; Dario Cozzi; Dirk Jungewelter; Sebastian Korf; Jens Hagemeyer; Mario Porrmann; Cinzia Bernardeschi (DTIS, 2014)

Reconfigurable high performance architectures: How much are they ready for safety-critical applications? - Davide Sabena; Luca Sterpone; Mario Schölzel; Tobias Koal; Heinrich Theodor Vierhaus; S. Wong; Robért Glein; Florian Rittner; C. Stender; Mario Porrmann; Jens Hagemeyer (ETS, 2014)

A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. - René Griessl; Meysam Peykanu; Jens Hagemeyer; Mario Porrmann; Stefan Krupop; Micha vor dem Berge; Thomas Kiesel; Wolfgang Christmann (EUC, 2014)

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture. - Boris Hübener; Gregor Sievers; Thorsten Jungeblut; Mario Porrmann; Ulrich Rückert 001 (EUC, 2014)

A 65 nm standard cell library for ultra low-power applications. - Marten Vohrmann; Saikat Chatterjee; Sven Lütkemeier; Thorsten Jungeblut; Mario Porrmann; Ulrich Rückert 001 (ECCTD, 2015)

Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI. - Gregor Sievers; Johannes Ax; Nils Kucza; Martin Flasskamp; Thorsten Jungeblut; Wayne Kelly; Mario Porrmann; Ulrich Rückert 001 (ISCAS, 2015)

Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI. - Gregor Sievers; Julian Daberkow; Johannes Ax; Martin Flasskamp; Wayne Kelly; Thorsten Jungeblut; Mario Porrmann; Ulrich Rückert 001 (MCSoC, 2015)

System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. - Johannes Ax; Gregor Sievers; Martin Flasskamp; Wayne Kelly; Thorsten Jungeblut; Mario Porrmann (NoCArc@MICRO, 2015)

A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. - Omar W. Ibraheem; Arif Irwansyah; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (ReConFig, 2015)

FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. - Arif Irwansyah; Omar W. Ibraheem; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (ReConFig, 2015)

The M2DC Project: Modular Microserver DataCentre. - Mariano Cecowski; Giovanni Agosta; Ariel Oleksiak; Michal Kierzynka; Micha vor dem Berge; Wolfgang Christmann; Stefan Krupop; Mario Porrmann; Jens Hagemeyer; René Griessl; Meysam Peykanu; Lennart Tigges; et al. (DSD, 2016)

Performance estimation of streaming applications for hierarchical MPSoCs. - Martin Flasskamp; Gregor Sievers; Johannes Ax; Christian Klarhorst; Thorsten Jungeblut; Wayne Kelly; Michael Thies; Mario Porrmann (RAPIDO@HiPEAC, 2016)

Data centres for IoT applications: The M2DC approach (Invited paper). - Michal Kierzynka; Ariel Oleksiak; Giovanni Agosta; Carlo Brandolese; William Fornaciari; Gerardo Pelosi; Micha vor dem Berge; Wolfgang Christmann; Stefan Krupop; Mariano Cecowski; Robert Plestenjak; Justin Cinkelj; et al. (SAMOS, 2016)

Reconfigurable vision processing system for player tracking in indoor sports. - Omar W. Ibraheem; Arif Irwansyah; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (DASIP, 2017)

From CPU to FPGA - Acceleration of self-organizing maps for data mining. - Jan Lachmair; Thomas Mieth; René Griessl; Jens Hagemeyer; Mario Porrmann (IJCNN, 2017)

Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs. - Johannes Ax; Nils Kucza; Marten Vohrmann; Thorsten Jungeblut; Mario Porrmann; Ulrich Rückert 001 (MCSoC, 2017)

FPGA-based multi-robot tracking. - Arif Irwansyah; Omar W. Ibraheem; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (J. Parallel Distributed Comput., 2017)

M2DC - Modular Microserver DataCentre with heterogeneous hardware. - Ariel Oleksiak; Michal Kierzynka; Wojciech Piatek; Giovanni Agosta; Alessandro Barenghi; Carlo Brandolese; William Fornaciari; Gerardo Pelosi; Mariano Cecowski; Robert Plestenjak; Justin Cinkelj; Mario Porrmann; et al. (Microprocess. Microsystems, 2017)

Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications. - Daniel Klimeck; Hanno Gerd Meyer; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (ASAP, 2018)

LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing. - Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel Jiménez-González; Carlos Álvarez 001; Behzad Salami 001; Sergi Madonar; Miquel Pericàs; Pedro Trancoso; et al. (CF, 2018)

An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods. - Cung Lian Sang; Michael Adams 002; Timm Hormann; Marc Hesse; Mario Porrmann; Ulrich Rückert 001 (IPIN, 2018)

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing. - Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel Jiménez-González; Carlos Álvarez 001; Behzad Salami 001; Sergi Madonar; Miquel Pericàs; Pedro Trancoso; et al. (SAMOS, 2018)

Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems. - Christian Klarhorst; Martin Flasskamp; Johannes Ax; Thorsten Jungeblut; Wayne Kelly; Mario Porrmann; Ulrich Rückert 001 (CoRR, 2018)

OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. - Dario Cozzi; Sebastian Korf; Luca Cassano; Jens Hagemeyer; Andrea Domenici; Cinzia Bernardeschi; Luca Sterpone; Mario Porrmann (IEEE Trans. Emerg. Top. Comput., 2018)

CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories. - Johannes Ax; Gregor Sievers; Julian Daberkow; Martin Flasskamp; Marten Vohrmann; Thorsten Jungeblut; Wayne Kelly; Mario Porrmann; Ulrich Rückert 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods. - Cung Lian Sang; Michael Adams 002; Timm Hörmann; Marc Hesse; Mario Porrmann; Ulrich Rückert 001 (Sensors, 2019)

FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports. - Omar W. Ibraheem; Arif Irwansyah; Jens Hagemeyer; Mario Porrmann; Ulrich Rückert 001 (J. Signal Process. Syst., 2019)

HATSDF SLAM - Hardware-accelerated TSDF SLAM for Reconfigurable SoCs. - Marc Eisoldt; Marcel Flottmann; Julian Gaal; Pascal Buschermöhle; Steffen Hinderink; Malte Hillmann; Adrian Nitschmann; Patrick Hoffmann; Thomas Wiemann; Mario Porrmann (ECMR, 2021)

Energy-efficient FPGA-accelerated LiDAR-based SLAM for embedded robotics. - Marcel Flottmann; Marc Eisoldt; Julian Gaal; Marc Rothmann; Marco Tassemeier; Thomas Wiemann; Mario Porrmann (FPT, 2021)

ReconfROS: Running ROS on Reconfigurable SoCs. - Marc Eisoldt; Steffen Hinderink; Marco Tassemeier; Marcel Flottmann; Juri Vana; Thomas Wiemann; Julian Gaal; Marc Rothmann; Mario Porrmann (DroneSE/RAPIDO@HiPEAC, 2021)

FAQ: A Flexible Accelerator for Q-Learning with Configurable Environment. - Marc Rothmann; Mario Porrmann (ASAP, 2022)

VEDLIoT: Very Efficient Deep Learning in IoT. - Martin Kaiser; René Griessl; Nils Kucza; Carola Haumann; Lennart Tigges; Kevin Mika; Jens Hagemeyer; Florian Porrmann; Ulrich Rückert 001; Micha vor dem Berge; Stefan Krupop; Mario Porrmann; et al. (DATE, 2022)

A Survey of Domain-Specific Architectures for Reinforcement Learning. - Marc Rothmann; Mario Porrmann (IEEE Access, 2022)

VEDLIoT: Very Efficient Deep Learning in IoT. - Martin Kaiser; René Griessl; Nils Kucza; Carola Haumann; Lennart Tigges; Kevin Mika; Jens Hagemeyer; Florian Porrmann; Ulrich Rückert 001; Micha vor dem Berge; Stefan Krupop; Mario Porrmann; et al. (CoRR, 2022)

A fully integrated system for hardware-accelerated TSDF SLAM with LiDAR sensors (HATSDF SLAM). - Marc Eisoldt; Julian Gaal; Thomas Wiemann; Marcel Flottmann; Marc Rothmann; Marco Tassemeier; Mario Porrmann (Robotics Auton. Syst., 2022)

ReconfROS: An approach for accelerating ROS nodes on reconfigurable SoCs. - Marc Eisoldt; Marcel Flottmann; Julian Gaal; Steffen Hinderink; Juri Vana; Marco Tassemeier; Marc Rothmann; Thomas Wiemann; Mario Porrmann (Microprocess. Microsystems, 2022)

VEDLIoT: Next generation accelerated AIoT systems and applications. - Kevin Mika; René Griessl; Nils Kucza; Florian Porrmann; Martin Kaiser; Lennart Tigges; Jens Hagemeyer; Pedro Trancoso; Muhammad Waqar Azhar; Fareed Qararyah; Stavroula Zouzoula; Jämes Ménétrey; et al. (CF, 2023)

Evaluation of heterogeneous AIoT Accelerators within VEDLIoT. - René Griessl; Florian Porrmann; Nils Kucza; Kevin Mika; Jens Hagemeyer; Martin Kaiser; Mario Porrmann; Marco Tassemeier; Marcel Flottmann; Fareed Qararyah; Muhammad Waqar Azhar; Pedro Trancoso; et al. (DATE, 2023)

ReDroSe - Reconfigurable Drone Setup for Resource-Efficient SLAM. - Sebastian Rahn; Philipp Gehricke; Can-Leon Petermöller; Eric Neumann; Philipp Schlinge; Leon Rabius; Henning Termühlen; Christopher Sieh; Marco Tassemeier; Thomas Wiemann; Mario Porrmann (DroneSE/RAPIDO@HiPEAC, 2023)

Towards 6D MCL for LiDARs in 3D TSDF Maps on Embedded Systems with GPUs. - Marc Eisoldt; Alexander Mock; Mario Porrmann; Thomas Wiemann (IRC, 2023)

FeatSense - A Feature-Based Registration Algorithm with GPU-Accelerated TSDF-Mapping Backend for NVIDIA Jetson Boards. - Julian Gaal; Thomas Wiemann; Alexander Mock; Mario Porrmann (IRC, 2023)

STANN - Synthesis Templates for Artificial Neural Network Inference and Training. - Marc Rothmann; Mario Porrmann (IWANN (1), 2023)

FPGA-based Acceleration of Deep Q-Networks with STANN-RL. - Marc Rothmann; Mario Porrmann (FMEC, 2024)

FPGA Acceleration of DL-Based Real-Time DC Series Arc Fault Detection. - Yufei Mao; Roland Weiss; Yi Zhang; Yu Li; Marc Rothmann; Mario Porrmann (IPDPS (Workshops), 2024)

HLS-Based Large Scale Self-Organizing Feature Maps. - Florian Porrmann; Jens Hagemeyer; Mario Porrmann (IEEE Access, 2024)

Efficient Global 6D Localization in 3D TSDF Maps Using Point-wise and Scan-wise Reduction Methods on Embedded GPUs. - Marc Eisoldt; Alexander Mock; Thomas Wiemann; Mario Porrmann (Int. J. Semantic Comput., 2025)