A high accuracy-low complexity model for CMOS delays. - Mario Roberto Casu; Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (ISCAS, 2000)

Synthesis of low-leakage PD-SOI circuits with body-biasing. - Mario R. Casu; Gianluca Piccinini; Guido Masera; Maurizio Zamboni (ISLPED, 2001)

Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. - Mario R. Casu; Philippe Flatresse (MTDT, 2002)

Clock Distribution Network Optimization under Self-Heating and Timing Constraints. - Mario R. Casu; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; M. M. Prono; Maurizio Zamboni (PATMOS, 2002)

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. - M. Addino; Mario R. Casu; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (PATMOS, 2003)

Effects of Temperature in Deep-Submicron Global Interconnect Optimization. - Mario R. Casu; Mariagrazia Graziano; Gianluca Piccinini; Guido Masera; Maurizio Zamboni (PATMOS, 2003)

Coupled electro-thermal modeling and optimization of clock networks. - Mario R. Casu; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (Microelectron. J., 2003)

A new approach to latency insensitive design. - Mario R. Casu; Luca Macchiarulo (DAC, 2004)

Issues in Implementing Latency Insensitive Protocols. - Mario R. Casu; Luca Macchiarulo (DATE, 2004)

On-Chip Transparent Wire Pipelining. - Mario R. Casu; Luca Macchiarulo (ICCD, 2004)

Floorplanning for throughput. - Mario R. Casu; Luca Macchiarulo (ISPD, 2004)

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. - Mariagrazia Graziano; Mario R. Casu; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (Microelectron. J., 2004)

An electromigration and thermal model of power wires for a priori high-level reliability prediction. - Mario R. Casu; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A New System Design Methodology for Wire Pipelined SoC. - Mario R. Casu; Luca Macchiarulo (DATE, 2005)

On the implementation of a transmitted-reference UWB receiver. - Mario R. Casu; Giuseppe Durisi; Sergio Benedetto (EUSIPCO, 2005)

Floorplan assisted data rate enhancement through wire pipelining: a real assessment. - Mario R. Casu; Luca Macchiarulo (ISPD, 2005)

Throughput-driven floorplanning with wire pipelining. - Mario R. Casu; Luca Macchiarulo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Implementation aspects of a transmitted-reference UWB receiver. - Mario R. Casu; Giuseppe Durisi (Wirel. Commun. Mob. Comput., 2005)

Implementation analysis of NoC: a MPSoC trace-driven approach. - Sergio Tota; Mario R. Casu; Luca Macchiarulo (ACM Great Lakes Symposium on VLSI, 2006)

Floorplanning With Wire Pipelining in Adaptive Communication Channels. - Mario R. Casu; Luca Macchiarulo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. - Marco Crepaldi; Mario R. Casu; Mariagrazia Graziano; Maurizio Zamboni (DATE, 2007)

The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology. - Sergio Tota; Mario R. Casu; Paolo Motto Ros; Massimo Ruo Roch; Maurizio Zamboni (SoC, 2007)

A methodology and a case-study for network-on-chip based MP-SoC architectures. - Sergio Tota; Mario R. Casu; Paolo Motto Ros; Massimo Ruo Roch; Maurizio Zamboni (Nano-Net, 2007)

Adaptive Latency-Insensitive Protocols. - Mario R. Casu; Luca Macchiarulo (IEEE Des. Test Comput., 2007)

A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver. - Mario R. Casu; Marco Crepaldi; Mariagrazia Graziano (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Fully Differential Digital CMOS UWB Pulse Generator. - Mario R. Casu; Mariagrazia Graziano; Maurizio Zamboni (Circuits Syst. Signal Process., 2009)

Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. - Mario R. Casu; Luca Macchiarulo (FMGALS@DATE, 2009)

A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. - Marco Crepaldi; Mario R. Casu; Mariagrazia Graziano; Maurizio Zamboni (Integr., 2009)

A Case Study for NoC-Based Homogeneous MPSoC Architectures. - Sergio Tota; Mario R. Casu; Massimo Ruo Roch; Luca Macchiarulo; Maurizio Zamboni (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming. - Mario R. Casu (ASYNC, 2010)

A flexible UWB Transmitter for breast cancer detection imaging systems. - Massimo Cutrupi; Marco Crepaldi; Mario R. Casu; Mariagrazia Graziano (DATE, 2010)

MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. - Sergio Tota; Mario R. Casu; Massimo Ruo Roch; Luca Rostagno; Maurizio Zamboni (DATE, 2010)

Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study. - Mario R. Casu; Stefano Colazzo; Paolo Mantovani (ACM Great Lakes Symposium on VLSI, 2011)

Half-buffer retiming and token cages for synchronous elastic circuits. - Mario R. Casu (IET Comput. Digit. Tech., 2011)

A NoC-based hybrid message-passing/shared-memory approach to CMP design. - Mario R. Casu; Massimo Ruo Roch; Sergio Tota; Maurizio Zamboni (Microprocess. Microsystems, 2011)

DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems. - Manoj Kumar Yadav; Mario R. Casu; Maurizio Zamboni (ASYNC, 2012)

Exploiting space diversity and Dynamic Voltage Frequency Scaling in multiplane Network-on-Chips. - Andrea Bianco; Paolo Giaccone; Mario Roberto Casu; Nanfang Li (GLOBECOM, 2012)

Breast cancer detection based on an UWB imaging system: Receiver design and simulations. - Xiaolu Guo; Mario R. Casu; Mariagrazia Graziano; Maurizio Zamboni (ICICDT, 2013)

Joint delay and power control in single-server queueing systems. - Andrea Bianco; Mario R. Casu; Paolo Giaccone; Marco Ricca (OnlineGreenComm, 2013)

UWB receiver for breast cancer detection: Comparison between two different approaches. - Xiaolu Guo; Mario R. Casu; Mariagrazia Graziano; Maurizio Zamboni (SoCC, 2013)

LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS. - Manoj Kumar Yadav; Mario R. Casu; Maurizio Zamboni (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection. - Francesco Colonna; Mariagrazia Graziano; Mario Roberto Casu; Xiaolu Guo; Maurizio Zamboni (VLSI Design, 2013)

Accelerator Memory Reuse in the Dark Silicon Era. - Emilio G. Cota; Paolo Mantovani; Michele Petracca; Mario R. Casu; Luca P. Carloni (IEEE Comput. Archit. Lett., 2014)

Simulation and design of an UWB imaging system for breast cancer detection. - Xiaolu Guo; Mario R. Casu; Mariagrazia Graziano; Maurizio Zamboni (Integr., 2014)

UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA? - Mario R. Casu; Francesco Colonna; Marco Crepaldi; Danilo Demarchi; Mariagrazia Graziano; Maurizio Zamboni (ACM Trans. Embed. Comput. Syst., 2014)

Microwave Imaging for Breast Cancer Detection: A COTS-Based Prototype. - Azzurra Pulimeno; Marco Vacca; Mario R. Casu; Jorge A. Tobon; Francesca Vipiana; Daniele Jahier Pagliari; Raffaele Solimene; Luca P. Carloni (ApplePies, 2015)

A low-cost, fast, and accurate microwave imaging system for breast cancer detection. - Daniele Jahier Pagliari; Azzurra Pulimeno; Marco Vacca; Jorge A. Tobon; Francesca Vipiana; Mario R. Casu; Raffaele Solimene; Luca P. Carloni (BioCAS, 2015)

Rate-based vs delay-based control for DVFS in NoC. - Mario R. Casu; Paolo Giaccone (DATE, 2015)

Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis. - Daniele Jahier Pagliari; Mario R. Casu; Luca P. Carloni (ICCD, 2015)

A synchronous latency-insensitive RISC for better than worst-case design. - Mario R. Casu; Paolo Mantovani (Integr., 2015)

Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy. - José V. Escamilla; Mario R. Casu; José Flich (MCSoC, 2016)

ICARO-PAPM: Congestion Management with Selective Queue Power-Gating. - José V. Escamilla; José Flich; Mario R. Casu (HPCS, 2017)

Power-performance assessment of different DVFS control policies in NoCs. - Mario R. Casu; Paolo Giaccone (J. Parallel Distributed Comput., 2017)

A COTS-Based Microwave Imaging System for Breast-Cancer Detection. - Mario R. Casu; Marco Vacca; Jorge A. Tobon; Azzurra Pulimeno; Imran Sarwar; Raffaele Solimene; Francesca Vipiana (IEEE Trans. Biomed. Circuits Syst., 2017)

Accelerators for Breast Cancer Detection. - Daniele Jahier Pagliari; Mario R. Casu; Luca P. Carloni (ACM Trans. Embed. Comput. Syst., 2017)

Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. - Giulia Santoro; Mario R. Casu; Valentino Peluso; Andrea Calimera; Massimo Alioto (DATE, 2018)

Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. - Giulia Santoro; Mario R. Casu; Valentino Peluso; Andrea Calimera; Massimo Alioto (ISCAS, 2018)

Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers. - Francesco Dell'Anna; Tao Dong 006; Ping Li 029; Yumei Wen; Mehdi Azadmehr; Mario R. Casu; Yngvar Berg (Sensors, 2018)

Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms. - Junnan Shan; Mario R. Casu; Jordi Cortadella; Luciano Lavagno; Mihai T. Lazarescu (DAC, 2019)

HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoC. - Mohammad Amir Mansoori; Mario R. Casu (NORCAS, 2019)

Efficient FPGA Implementation of PCA Algorithm for Large Data using High Level Synthesis. - Mohammad Amir Mansoori; Mario R. Casu (PRIME, 2019)

A Machine-Learning Based Microwave Sensing Approach to Food Contaminant Detection. - Luca Urbinati; Marco Ricci 004; Giovanna Turvani; Jorge A. Tobon Vasquez; Francesca Vipiana; Mario R. Casu (ISCAS, 2020)

A Prototype Microwave System for 3D Brain Stroke Imaging. - Jorge A. Tobon; Rosa Scapaticci; Giovanna Turvani; Gennaro Bellizzi; David O. Rodriguez-Duarte; Nadine Joachimowicz; Bernard Duchêne; Enrico Tedeschi; Mario R. Casu; Lorenzo Crocco; Francesca Vipiana (Sensors, 2020)

Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms. - Junnan Shan; Mihai T. Lazarescu; Jordi Cortadella; Luciano Lavagno; Mario R. Casu (IEEE Trans. Circuits Syst., 2020)

Efficient Training and Hardware Co-design of Machine Learning Models. - Mohammad Amir Mansoori; Mario R. Casu (ApplePies, 2021)

FPGA Acceleration of 3D FDTD for Multi- Antennas Microwave Imaging Using HLS. - Mohammad Amir Mansoori; Pan Lu; Mario R. Casu (IEEE Access, 2021)

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs. - Osama Bin Tariq; Junnan Shan; Georgios Floros 002; Christos P. Sotiriou; Mario R. Casu; Mihai Teodor Lazarescu; Luciano Lavagno (IEEE Access, 2021)

Machine-Learning-Based Microwave Sensing: A Case Study for the Food Industry. - Marco Ricci 004; Bernardita Stitic; Luca Urbinati; Giuseppe Di Guglielmo; Jorge A. Tobon Vasquez; Luca P. Carloni; Francesca Vipiana; Mario R. Casu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms. - Junnan Shan; Mihai T. Lazarescu; Jordi Cortadella; Luciano Lavagno; Mario R. Casu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Multi-objective Framework for Training and Hardware Co-optimization in FPGAs. - Mohammad Amir Mansoori; Mario R. Casu (ApplePies, 2022)

A Reconfigurable 2D-Convolution Accelerator for DNNs Quantized with Mixed-Precision. - Luca Urbinati; Mario R. Casu (ApplePies, 2022)

HLS-based dataflow hardware architecture for Support Vector Machine in FPGA. - Mohammad Amir Mansoori; Mario R. Casu (ISCAS, 2022)

A Reconfigurable Depth-Wise Convolution Module for Heterogeneously Quantized DNNs. - Luca Urbinati; Mario R. Casu (ISCAS, 2022)

Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms. - Junnan Shan; Mihai T. Lazarescu; Jordi Cortadella; Luciano Lavagno; Mario R. Casu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Design-Space Exploration of Mixed-precision DNN Accelerators based on Sum-Together Multipliers. - Luca Urbinati; Mario R. Casu (PRIME, 2023)

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops. - Filippo Minnella; Jordi Cortadella; Mario R. Casu; Mihai T. Lazarescu; Luciano Lavagno (IEEE Access, 2023)

To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration. - Fabrizio Ottati; Chang Gao 002; Qinyu Chen; Giovanni Brignone; Mario R. Casu; Jason K. Eshraghian; Luciano Lavagno (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML Workloads. - Edward Manca; Luca Urbinati; Mario R. Casu (DATE, 2024)

WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU). - Klaus Hofmann; Ferdinand Keil; David Riehl; Alicja Michalowska-Forsyth; Nikolaus Czepl; Sarah Woywod; Dominik Zupan; Mario R. Casu; Carlo Ricciardi; Massimo Violante; Mariagrazia Graziano; Yuri Ardesi; et al. (FIE, 2024)

High-Level Design of Precision-Scalable DNN Accelerators Based on Sum-Together Multipliers. - Luca Urbinati; Mario R. Casu (IEEE Access, 2024)

Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark. - Lorenzo Lagostina; Filippo Minnella; Jordi Cortadella; Mario R. Casu; Mihai T. Lazarescu; Luciano Lavagno (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. - Roberto Bosio; Filippo Minnella; Teodoro Urso; Mario R. Casu; Luciano Lavagno; Mihai T. Lazarescu; Paolo Pasini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)