7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kouno; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (ISSCC, 2015)

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kono; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (IEEE J. Solid State Circuits, 2016)

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi 004; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (ISSCC, 2019)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput. - Mario Sako; T. Nakajima; Fumihiro Kono; Takeshi Nakano; Masaki Fujiu; Junji Musha; Dai Nakamura; Naoaki Kanagawa; Yutaka Shimizu; Kosuke Yanagidaira; Tetsuaki Utsumi; T. Kawano; et al. (VLSI Technology and Circuits, 2023)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)