Testability of path history memories with register-exchange architecture used in Viterbi-decoders. - Stefan R. Meier; Mario Steinert; Steffen Buch (ISCAS (3), 2002)

RTL Processor Synthesis for Architecture Exploration and Implementation. - Oliver Schliebusch; Anupam Chattopadhyay; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Mario Steinert; Gunnar Braun; Achim Nohl (DATE, 2004)

Power consumption optimization for low latency Viterbi Decoder. - Mario Steinert; Stefano Marsili (ISCAS (2), 2004)

A power dissipation comparison of ALU-architectures for ASIPs. - Vijayakumar Kalyanaraman; Matthias Müller 002; Sven Simon 001; Mario Steinert; Holger Gryska (ECCTD, 2005)

Power reduction of ASIPs by distributing the workload on several ASIP-instances. - Vijayakumar Kalyanaraman; Matthias Müller 002; Sven Simon 001; Mario Steinert; Holger Gryska (ECCTD, 2005)