Understanding Retiming Through Maximum Average-Weight Cycles. - Marios C. Papaefthymiou (SPAA, 1991)

TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. - Marios C. Papaefthymiou; Keith H. Randall (DAC, 1993)

Implementing parallel shortest-paths algorithms. - Marios C. Papaefthymiou; Joseph Rodrigue (Parallel Algorithms, 1994)

Memory Assignment for Multiprocessor Caches through Grey Coloring. - Anant Agarwal; John V. Guttag; Christoforos N. Hadjicostis; Marios C. Papaefthymiou (PARLE, 1994)

Understanding Retiming Through Maximum Avarage-Delay Cycles. - Marios C. Papaefthymiou (Math. Syst. Theory, 1994)

Precomputation-based sequential logic optimization for low power. - Mazhar Alidina; José Monteiro 001; Srinivas Devadas; Abhijit Ghosh; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Efficient retiming under a general delay model. - Kumar N. Lalgudi; Marios C. Papaefthymiou (ARVLSI, 1995)

DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. - Kumar N. Lalgudi; Marios C. Papaefthymiou (DAC, 1995)

Optimizing Systems for Effective Block-Processing: The k-Delay Problem. - Kumar N. Lalgudi; Marios C. Papaefthymiou; Miodrag Potkonjak (DAC, 1996)

Fixed-phase retiming for low power design. - Marios C. Papaefthymiou; Kumar N. Lalgudi (ISLPED, 1996)

A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. - Fang Wang; Hubertus Franke; Marios C. Papaefthymiou; Pratap Pattnaik; Larry Rudolph; Mark S. Squillante (JSSPP, 1996)

An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. - Mark S. Squillante; Fang Wang; Marios C. Papaefthymiou (SPAA, 1996)

Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. - Mark S. Squillante; Fang Wang; Marios C. Papaefthymiou (Perform. Evaluation, 1996)

Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. - Fang Wang; Marios C. Papaefthymiou; Mark S. Squillante (JSSPP, 1997)

Computing Strictly-Second Shortest Paths. - Kumar N. Lalgudi; Marios C. Papaefthymiou (Inf. Process. Lett., 1997)

Optimizing two-phase, level-clocked circuitry. - Alexander T. Ishii; Charles E. Leiserson; Marios C. Papaefthymiou (J. ACM, 1997)

Retiming edge-triggered circuits under general delay models. - Kumar N. Lalgudi; Marios C. Papaefthymiou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Asymptotically efficient retiming under setup and hold constraints. - Marios C. Papaefthymiou (ICCAD, 1998)

True single-phase energy-recovering logic for low-power, high-speed VLSI. - Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 1998)

Maximizing Performance by Retiming and Clock Skew Scheduling. - Xun Liu; Marios C. Papaefthymiou; Eby G. Friedman (DAC, 1999)

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. - Xun Liu; Marios C. Papaefthymiou; Eby G. Friedman (DATE, 1999)

Analytical macromodeling for high-level power estimation. - Giuseppe Bernacchia; Marios C. Papaefthymiou (ICCAD, 1999)

Single-phase source-coupled adiabatic logic. - Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 1999)

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors. - Inki Hong; Miodrag Potkonjak; Marios C. Papaefthymiou (Des. Autom. Embed. Syst., 1999)

Symbolic debugging of globally optimized behavioral specifications. - Inki Hong; Darko Kirovski; Miodrag Potkonjak; Marios C. Papaefthymiou (ASP-DAC, 2000)

Dynamic Memory Design for Low Data-Retention Power. - Joohee Kim; Marios C. Papaefthymiou (PATMOS, 2000)

Optimizing computations for effective block-processing. - Kumar N. Lalgudi; Marios C. Papaefthymiou; Miodrag Potkonjak (ACM Trans. Design Autom. Electr. Syst., 2000)

Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (ARVLSI, 2001)

A True Single-Phase 8-bit Adiabatic Multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (DAC, 2001)

A static power estimation methodolodgy for IP-based design. - Xun Liu; Marios C. Papaefthymiou (DATE, 2001)

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. - Dimitrios Velenis; Eby G. Friedman; Marios C. Papaefthymiou (ISCAS (4), 2001)

A resonant clock generator for single-phase adiabatic systems. - Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 2001)

Symbolic debugging of embedded hardware and software. - Farinaz Koushanfar; Darko Kirovski; Inki Hong; Miodrag Potkonjak; Marios C. Papaefthymiou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

True single-phase adiabatic circuitry. - Suhwan Kim 001; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Design of a high-throughput low-power IS95 Viterbi decoder. - Xun Liu; Marios C. Papaefthymiou (DAC, 2002)

Incorporation of input glitches into power macromodeling. - Xun Liu; Marios C. Papaefthymiou (ISCAS (4), 2002)

Energy recovering static memory. - Joohee Kim; Conrad H. Ziesler; Marios C. Papaefthymiou (ISLPED, 2002)

Retiming and clock scheduling for digital circuit optimization. - Xun Liu; Marios C. Papaefthymiou; Eby G. Friedman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

HyPE: hybrid power estimation for IP-based programmable systems. - Xun Liu; Marios C. Papaefthymiou (ASP-DAC, 2003)

Reduced Delay Uncertainty in High Performance Clock Distribution Networks. - Dimitrios Velenis; Marios C. Papaefthymiou; Eby G. Friedman (DATE, 2003)

A 225 MHz resonant clocked ASIC chip. - Conrad H. Ziesler; Joohee Kim; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ISLPED, 2003)

Energy Recovering ASIC Design. - Conrad H. Ziesler; Joohee Kim; Marios C. Papaefthymiou (ISVLSI, 2003)

Fine-grain real-time reconfigurable pipelining. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IBM J. Res. Dev., 2003)

Block-based multiperiod dynamic memory design for low data-retention power. - Joohee Kim; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A true single-phase energy-recovery multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Design of a 20-mb/s 256-state Viterbi decoder. - Xun Liu; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2003)

An Algorithm for Geometric Load Balancing with Two Constraints. - Jiyoun Kim; Marios C. Papaefthymiou; Athar B. Tayyab (IPDPS, 2004)

Empirical evaluation of timing and power in resonant clock distribution. - Juang-Ying Chueh; Conrad H. Ziesler; Marios C. Papaefthymiou (ISCAS (2), 2004)

Constant-load energy recovery memory for efficient high-speed operation. - Joohee Kim; Marios C. Papaefthymiou (ISLPED, 2004)

Experimental Evaluation of Resonant Clock Distribution. - Juang-Ying Chueh; Conrad H. Ziesler; Marios C. Papaefthymiou (ISVLSI, 2004)

A synchronous interface for SoCs with multiple clock domains. - Visvesh S. Sathe 001; Conrad H. Ziesler; Marios C. Papaefthymiou; Suhwan Kim 001; Stephen V. Kosonocky (SoCC, 2004)

Clock tree layout design for reduced delay uncertainty. - Dimitrios Velenis; Marios C. Papaefthymiou; Eby G. Friedman (SoCC, 2004)

A Markov chain sequence generator for power macromodeling. - Xun Liu; Marios C. Papaefthymiou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Fast, efficient, recovering, and irreversible. - Visvesh S. Sathe 001; Juang-Ying Chueh; Joohee Kim; Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (Conf. Computing Frontiers, 2005)

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. - Xun Liu; Yuantao Peng; Marios C. Papaefthymiou (DATE, 2005)

A GHz-class charge recovery logic. - Visvesh S. Sathe 001; Marios C. Papaefthymiou; Conrad H. Ziesler (ISLPED, 2005)

Two-Phase Resonant Clock Distribution. - Juang-Ying Chueh; Marios C. Papaefthymiou; Conrad H. Ziesler (ISVLSI, 2005)

Boost Logic: A High Speed Energy Recovery Circuit Family. - Visvesh S. Sathe 001; Marios C. Papaefthymiou; Conrad H. Ziesler (ISVLSI, 2005)

Multi-Session Partitioning for Parallel Timing Optimization. - Jiyoun Kim; José Neves 002; Marios C. Papaefthymiou (PDCAT, 2005)

Charge-Recovery Computing on Silicon. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IEEE Trans. Computers, 2005)

HyPE: hybrid power estimation for IP-based systems-on-chip. - Xun Liu; Marios C. Papaefthymiou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. - Juang-Ying Chueh; Visvesh S. Sathe 001; Marios C. Papaefthymiou (CICC, 2006)

Parallelizing post-placement timing optimization. - Jiyoun Kim; Marios C. Papaefthymiou; José Luis Neves (IPDPS, 2006)

Practical repeater insertion for low power: what repeater library do we need? - Xun Liu; Yuantao Peng; Marios C. Papaefthymiou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. - Visvesh S. Sathe 001; Jerry C. Kao; Marios C. Papaefthymiou (CICC, 2007)

Skew spreading for peak current reduction. - Zhengtao Yu 002; Marios C. Papaefthymiou; Xun Liu (ACM Great Lakes Symposium on VLSI, 2007)

Energy-Efficient GHz-Class Charge-Recovery Logic. - Visvesh S. Sathe 001; Juang-Ying Chueh; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2007)

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; Marios C. Papaefthymiou (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Resonant-Clock Latch-Based Design. - Visvesh S. Sathe 001; Jerry C. Kao; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2008)

A resonant-clock 200MHz ARM926EJ-STM microcontroller. - Alexander T. Ishii; Jerry C. Kao; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ESSCIRC, 2009)

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. - Jerry C. Kao; Wei-Hsiang Ma; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ESSCIRC, 2009)

187 MHz Subthreshold-Supply Charge-Recovery FIR. - Wei-Hsiang Ma; Jerry C. Kao; Visvesh S. Sathe 001; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2010)

A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. - Wei-Hsiang Ma; Jerry C. Kao; Marios C. Papaefthymiou (ESSCIRC, 2011)

Computational sprinting. - Arun Raghavan; Yixin Luo; Anuj Chandawalla; Marios C. Papaefthymiou; Kevin P. Pipe; Thomas F. Wenisch; Milo M. K. Martin (HPCA, 2012)

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. - Jerry C. Kao; Wei-Hsiang Ma; Visvesh S. Sathe 001; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Computational sprinting on a hardware/software testbed. - Arun Raghavan; Laurel Emurian; Lei Shao; Marios C. Papaefthymiou; Kevin P. Pipe; Thomas F. Wenisch; Milo M. K. Martin (ASPLOS, 2013)

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. - Visvesh S. Sathe 001; Srikanth Arekapudi; Alexander T. Ishii; Charles Ouyang; Marios C. Papaefthymiou; Samuel Naffziger (IEEE J. Solid State Circuits, 2013)

Utilizing Dark Silicon to Save Energy with Computational Sprinting. - Arun Raghavan; Laurel Emurian; Lei Shao; Marios C. Papaefthymiou; Kevin P. Pipe; Thomas F. Wenisch; Milo M. K. Martin (IEEE Micro, 2013)

Designing for Responsiveness with Computational Sprinting. - Arun Raghavan; Yixin Luo; Anuj Chandawalla; Marios C. Papaefthymiou; Kevin P. Pipe; Thomas F. Wenisch; Milo M. K. Martin (IEEE Micro, 2013)

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. - Tai-Chuan Ou; Zhengya Zhang; Marios C. Papaefthymiou (ISSCC, 2014)

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. - Seyong Ahn; Minseok Kang; Marios C. Papaefthymiou; Taewhan Kim 001 (ASP-DAC, 2015)

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. - Tai-Chuan Ou; Zhengya Zhang; Marios C. Papaefthymiou (A-SSCC, 2015)

1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. - Shengshuo Lu; Zhengya Zhang; Marios C. Papaefthymiou (VLSIC, 2015)

A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh. - Shengshuo Lu; Zhengya Zhang; Marios C. Papaefthymiou (A-SSCC, 2016)

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. - Seyong Ahn; Minseok Kang; Marios C. Papaefthymiou; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices. - Shengshuo Lu; Zhengya Zhang; Marios C. Papaefthymiou (A-SSCC, 2017)

20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. - Hsi-Shou Wu; Zhengya Zhang; Marios C. Papaefthymiou (ISSCC, 2017)

A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. - Hsi-Shou Wu; Zhengya Zhang; Marios C. Papaefthymiou (ESSCIRC, 2018)

Rethinking Numerical Representations for Deep Neural Networks. - Parker Hill; Babak Zamirai; Shengshuo Lu; Yu-Wei Chao; Michael Laurenzano; Mehrzad Samadi; Marios C. Papaefthymiou; Scott A. Mahlke; Thomas F. Wenisch; Jia Deng 001; Lingjia Tang; Jason Mars (CoRR, 2018)