A Co-Design Methodology Based on Formal Specification and High-level Estimation. - Carlos Carreras; Juan Carlos López 001; María Luisa López Vallejo; Luis Sánchez 001; Carlos Delgado Kloos; Natividad Martínez Madrid (CODES, 1996)

A Knowledge-based System for Hardware-Software Partitioning. - Marisa Luisa López-Vallejo; Carlos Angel Iglesias; Juan Carlos López 001 (DATE, 1998)

Applying the Propose&Revise Strategy to the Hardware-Software Partitioning Problem. - Marisa Luisa López-Vallejo; Carlos Angel Iglesias; Juan Carlos López 001 (IEA/AIE (Vol. 1), 1998)

Hardware-Software Prototyping from LOTOS. - Luis Sánchez Fernández 001; Gernot Koch; Natividad Martínez Madrid; María Luisa López Vallejo; Carlos Delgado Kloos; Wolfgang Rosenstiel (Des. Autom. Embed. Syst., 1998)

Hardware-Software Partitioning at the Knowledge Level. - Marisa Luisa López-Vallejo; Juan Carlos López 001; Carlos Angel Iglesias (Appl. Intell., 1999)

Constraint-Driven System Partitioning. - Marisa Luisa López-Vallejo; Jesús Grajal; Juan Carlos López 001 (DATE, 2000)

ED68K. A design framework for the development of digital systems based on MC68000. - Marisa Luisa López-Vallejo; J. M. Fernández Freire; J. Colás (Computers and Education. Towards an Interconnected Society, 2001)

Block processing technique for low power turbo decoder design. - Inkyu Lee; Marisa López-Vallejo; Syed Aon Mujtaba (VTC Spring, 2002)

State Space Compression in History Driven Quasi-Static Scheduling. - Antonio G. Lomeña; Marisa López-Vallejo; Yosinori Watanabe; Alex Kondratyev (Embedded Software for SoC, 2003)

Energy Aware Register File Implementation through Instruction Predecode. - José L. Ayala; Marisa Luisa López-Vallejo; Alexander V. Veidenbaum; Carlos A. Lopez (ASAP, 2003)

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. - Antonio G. Lomeña; Marisa Luisa López-Vallejo; Yosinori Watanabe; Alex Kondratyev (DATE, 2003)

A Unified Framework for Power-Aware Design of Embedded Systems. - José L. Ayala; Marisa Luisa López-Vallejo (PATMOS, 2003)

Power-Aware Compilation for Register File Energy Reduction. - José L. Ayala; Alexander V. Veidenbaum; Marisa Luisa López-Vallejo (Int. J. Parallel Program., 2003)

On the hardware-software partitioning problem: System modeling and partitioning techniques. - Marisa Luisa López-Vallejo; Juan Carlos López 001 (ACM Trans. Design Autom. Electr. Syst., 2003)

Improving IP core reuse through the application of the meta-language xHDL. - Marcos M. A. Sanchez; Fernandez Herrero; Marisa López-Vallejo (FDL, 2004)

Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. - José Luis Ayala; Marisa López-Vallejo (Power-aware Computing Systems, 2005)

Integrating functional and power simulation in embedded systems design. - José Luis Ayala; Marisa López-Vallejo (J. Embed. Comput., 2005)

State-of-the-Art SoC Communication Architectures. - Davide Bertozzi; Luca Benini; Marisa López-Vallejo; José L. Ayala (Embedded Systems Handbook, 2005)

New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. - Pablo Ituero; Marisa López-Vallejo (ASAP, 2006)

Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. - Miguel A. Sánchez Marcos; Mario Garrido; Marisa López-Vallejo; Carlos A. López-Barrio (FPT, 2006)

Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors. - José Luis Ayala; Cándido Méndez; Marisa López-Vallejo (ICECS, 2006)

Leakage Energy Reduction in Banked Content Addressable Memories. - Pedro Echeverría; José Luis Ayala; Marisa López-Vallejo (ICECS, 2006)

Compiler-Driven Leakage Energy Reduction in Banked Register Files. - David Atienza; Praveen Raghavan; José L. Ayala; Giovanni De Micheli; Francky Catthoor; Diederik Verkest; Marisa López-Vallejo (PATMOS, 2006)

Target Independent Thermal Modeling for Embedded Processors. - Cándido Méndez; José Luis Ayala; Marisa López-Vallejo (IES, 2006)

Thermal Characterization and Thermal Management in Processor-Based Systems. - José Luis Ayala; Anya Apavatjrut; David Atienza; Marisa López-Vallejo; Carlos A. López-Barrio (Power-aware Computing Systems, 2007)

Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. - Pablo Ituero; Gorka Landaburu; Javier Del Ser; Marisa López-Vallejo; Pedro M. Crespo; Vicente Atxa; Jon Altuna (ICESS, 2007)

Leakage-based On-Chip Thermal Sensor for CMOS Technology. - Pablo Ituero; José L. Ayala; Marisa López-Vallejo (ISCAS, 2007)

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. - Praveen Raghavan; José L. Ayala; David Atienza; Francky Catthoor; Giovanni De Micheli; Marisa López-Vallejo (ISCAS, 2007)

Energy-aware compilation and hardware design for VLIW embedded systems. - José L. Ayala; Marisa López-Vallejo; David Atienza; Praveen Raghavan; Francky Catthoor; Diederik Verkest (Int. J. Embed. Syst., 2007)

An FPGA run-time parameterisable Log-Normal Random Number Generator. - Pedro Echeverría; David B. Thomas; Marisa López-Vallejo; Wayne Luk (ARC, 2008)

Designing Highly Parameterized Hardware using xHdl. - Miguel Angel Sánchez; Pedro Echeverría; Francisco Mansilla; Marisa López-Vallejo (FDL, 2008)

A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. - Angel Fernandez Herrero; Ignacio Elguezábal; Marisa López-Vallejo (e-Learning, 2008)

Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach. - Pedro Echeverría; Marisa López-Vallejo; Jose María Pesquero (ICECS, 2008)

Experimental methodology for power characterization of FPGAs. - Ignacio Herrera-Alzu; Miguel Angel Sánchez; Marisa López-Vallejo; Pedro Echeverría (ICECS, 2008)

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. - José Luis Ayala; Marisa López-Vallejo; Carlos A. López-Barrio; Alexander V. Veidenbaum (Int. J. Embed. Syst., 2008)

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. - David Atienza; Praveen Raghavan; José Luis Ayala; Giovanni De Micheli; Francky Catthoor; Diederik Verkest; Marisa López-Vallejo (Integr., 2008)

Power Considerations in Banked CAMs: A Leakage Reduction Approach. - Pedro Echeverría Aramendi; José L. Ayala; Marisa López-Vallejo (VLSI Design, 2008)

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs. - José L. Ayala; Marisa López-Vallejo; Davide Bertozzi; Luca Benini (Embedded Systems Design and Verification, 2009)

Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs. - Pedro Echeverría; Marisa López-Vallejo; Walter Bolognesi; Carlos A. López-Barrio (ICECS, 2009)

Thermal analysis and modeling of embedded processors. - José Luis Ayala; Cándido Méndez; Marisa López-Vallejo (Comput. Electr. Eng., 2010)

On-chip Monitoring: A Light-Weight Interconnection Network Approach. - Pablo Ituero; Marisa López-Vallejo; Miguel A. Sánchez Marcos; Carlos Gómez Osuna (DSD, 2011)

Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications. - Jesús Grajal; Omar A. Yeste Ojeda; Miguel Angel Sánchez; Mario Garrido; Marisa López-Vallejo (EUSIPCO, 2011)

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. - Ignacio Herrera-Alzu; Marisa López-Vallejo (PATMOS, 2011)

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. - Pedro Echeverría; Marisa López-Vallejo (Microprocess. Microsystems, 2011)

Improving Hardware Reuse through XML-based Interface Encapsulation. - Miguel Angel Sánchez; Marisa López-Vallejo; Carlos Angel Iglesias; Carlos A. López-Barrio (ICECCS, 2012)

A monitoring infrastructure for FPGA self-awareness and dynamic adaptation. - Carlos Gómez Osuna; Miguel A. Sánchez Marcos; Pablo Ituero; Marisa López-Vallejo (ICECS, 2012)

Hardware Reuse Improvement through the Domain Specific Language dHDL. - Miguel Angel Sánchez; Marisa López-Vallejo; Carlos Angel Iglesias (ISPA, 2012)

A Low-Area Reference-Free Power Supply Sensor. - Carlos Benito; Pablo Ituero; Marisa López-Vallejo (DSD, 2013)

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. - Pablo Royer; Marisa López-Vallejo (ACM Great Lakes Symposium on VLSI, 2013)

A 0.0016 mm2 0.64 nJ Leakage-Based CMOS Temperature Sensor. - Pablo Ituero; Marisa López-Vallejo; Carlos A. López-Barrio (Sensors, 2013)

Floating-Point Exponentiation Units for Reconfigurable Computing. - Florent de Dinechin; Pedro Echeverría; Marisa López-Vallejo; Bogdan Pasca 001 (ACM Trans. Reconfigurable Technol. Syst., 2013)

High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator. - Pedro Echeverría; Marisa López-Vallejo (J. Signal Process. Syst., 2013)

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs). - Carlos Gómez Osuna; Pablo Ituero; Marisa López-Vallejo (Sensors, 2014)

A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs. - Ignacio Herrera-Alzu; Marisa López-Vallejo; C. Gil Soriano (DFTS, 2015)

A thermal adaptive scheme for reliable write operation on RRAM based architectures. - Fernando García-Redondo; Marisa López-Vallejo; Pablo Ituero (ICCD, 2015)

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm. - Pablo Royer; Fernando García-Redondo; Marisa López-Vallejo (NANOARCH, 2015)

Real-time low-complexity automatic modulation classifier for pulsed radar signals. - Victor Iglesias; Jesús Grajal; Pablo Royer; Miguel A. Sánchez Marcos; Marisa López-Vallejo; Omar A. Yeste Ojeda (IEEE Trans. Aerosp. Electron. Syst., 2015)

An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle. - Javier Agustin; Marisa López-Vallejo (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms. - Victor Iglesias; Jesús Grajal; Miguel A. Sánchez Marcos; Marisa López-Vallejo (IEEE Trans. Instrum. Meas., 2015)

A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators. - Javier Agustin; Marisa Luisa López-Vallejo (ISCAS, 2016)

Reliable design methodology: The combined effect of radiation, variability and temperature. - Fernando García-Redondo; Marisa López-Vallejo; Hernan Aparicio; Pablo Ituero (SMACD, 2016)

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds. - Fernando García-Redondo; Robert P. Gowers; Albert Crespo-Yepes; Marisa López-Vallejo; Liudi Jiang (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model. - Jose M. Nadal-Serrano; Marisa López-Vallejo (IEEE Trans. Parallel Distributed Syst., 2016)

Advanced integration of variability and degradation in RRAM SPICE compact models. - Fernando García-Redondo; Marisa López-Vallejo; Carlos A. López-Barrio (SMACD, 2017)

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges. - Fernando García-Redondo; Pablo Royer; Marisa López-Vallejo; Hernan Aparicio; Pablo Ituero; Carlos A. López-Barrio (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. - Mario Garrido; Miguel Angel Sánchez; María Luisa López Vallejo; Jesús Grajal (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Performance-oriented Implementation of Hilbert Filters on FPGAs. - Daniel Fortun; Carlos Garcia de la Cueva; Jesús Grajal; Marisa López-Vallejo; Carlos A. López-Barrio (DCIS, 2018)

A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications. - Asghar Bahramali; Marisa López-Vallejo (PATMOS, 2018)

Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks. - Fernando García-Redondo; Marisa López-Vallejo (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations. - Mario Garrido; Marisa Luisa López-Vallejo; Sau-Gee Chen (J. Signal Process. Syst., 2018)

A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology. - Asghar Bahramali; Marisa López-Vallejo; Carlos A. López-Barrio (DCIS, 2019)

Temperature-aware writing architecture for multilevel memristive cells. - Amadeo de Gracia Herranz; Marisa López-Vallejo (PATMOS, 2019)

A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage. - Asghar Bahramali; Marisa López-Vallejo (Integr., 2019)

Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms. - Samuel López Asunción; Marisa López-Vallejo; Jesús Grajal (DCIS, 2020)

An ultra-low power deep sub-micron fast start-up circuit with added line regulation. - Asghar Bahramali; Marisa López-Vallejo; Carlos A. López-Barrio (DCIS, 2020)

Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations. - Amadeo de Gracia Herranz; Marisa López-Vallejo (Integr., 2020)

A 65nm Current and Voltage Reference with Improved Line Regulation for Implantable Biosensors. - Javier De Mena Pacheco; Marisa López-Vallejo (DCIS, 2021)

Time to Digital Sensing for Multilevel RRAM Cells. - Amadeo de Gracia Herranz; Marisa López-Vallejo (IEEE Access, 2021)

Data Synchronization in Non-Uniform Latency Custom DSP Designs. - Samuel López Asunción; Pablo Ituero; Marisa López-Vallejo; Jesús Grajal (DCIS, 2022)

Reference-free power supply monitor with enhanced robustness against process and temperature variations. - Hernan Aparicio; Pablo Ituero; Marisa López-Vallejo (Integr., 2022)

Power-Efficient Implementation of Ternary Neural Networks in Edge Devices. - Miguel Molina; Javier Mendez 001; Diego Pedro Morales; Encarnación Castillo; Marisa López-Vallejo; Manuel Pegalajar (IEEE Internet Things J., 2022)

Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. - Alba Páez-Montoro; Javier De Mena Pacheco; Marisa López-Vallejo; Celia López-Ongil; Susana Patón (DCIS, 2023)

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond. - Víctor Manuel Bautista; Mario Garrido; Marisa López-Vallejo (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Lightweight Analog RFID Front-End for Interfacing Sensors. - Javier De Mena Pacheco; Borja Gutiérrez De Cabiedes; Amadeo de Gracia Herranz; Marisa López-Vallejo (DCIS, 2024)

Drift Compensation in Multilevel PCM for in-Memory Computing Accelerators. - L. Pistolesi; Artem Glukhov; Amadeo de Gracia Herranz; Marisa López-Vallejo; Marcella Carissimi; Marco Pasotti; Pier Luigi Rolandi; Andrea Redaelli; I. Muñoz-Martín; S. Bianchi; Andrea Bonfanti; Daniele Ielmini (IRPS, 2024)

Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction. - Oliver Schrape; Anselm Breitenreiter; Li Lu; Marko S. Andjelkovic; Ernesto Pun-Garcia; Marisa López-Vallejo; Milos Krstic (NorCAS, 2024)

Design and Implementation of a Real-Time Low-Latency Automatic Modulation Classifier. - Samuel López Asunción; Jorge Gonzalez-Lopez; Carlos Garcia de la Cueva; Marisa López-Vallejo; Jesús Grajal (IEEE Trans. Instrum. Meas., 2025)

A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems. - Javier De Mena Pacheco; Juan M. Carrillo; Tomas Palacios; Marisa López-Vallejo (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)