Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. - Marius Evers; Po-Yung Chang; Yale N. Patt (ISCA, 1996)

One Billion Transistors, One Uniprocessor, One Chip. - Yale N. Patt; Sanjay J. Patel; Marius Evers; Daniel H. Friendly; Jared Stark (Computer, 1997)

Improving branch prediction accuracy by reducing pattern history table interference. - Po-Yung Chang; Marius Evers; Yale N. Patt (Int. J. Parallel Program., 1997)

Variable Length Path Branch Prediction. - Jared Stark; Marius Evers; Yale N. Patt (ASPLOS, 1998)

An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. - Marius Evers; Sanjay J. Patel; Robert S. Chappell; Yale N. Patt (ISCA, 1998)

Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. - Sanjay J. Patel; Marius Evers; Yale N. Patt (ISCA, 1998)

Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. - Eric Hao; Po-Yung Chang; Marius Evers; Yale N. Patt (Int. J. Parallel Program., 1998)

Improving branch prediction by understanding branch behavior. - Marius Evers (2000)

Understanding branches and designing branch predictors for high-performance microprocessors. - Marius Evers; Tse-Yu Yeh (Proc. IEEE, 2001)

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. - Jeegar Tilak Shah; Marius Evers; Jeff Trull; Alper Halbutogullari (ISPD, 2007)