Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. - Marius Meyer; Tobias Kenter; Christian Plessl (H2RC@SC, 2020)

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite. - Marius Meyer; Tobias Kenter; Christian Plessl (CoRR, 2020)

Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. - Marius Meyer (HEART, 2021)

In-depth FPGA accelerator performance evaluation with single node benchmarks from the HPC challenge benchmark suite for Intel and Xilinx FPGAs using OpenCL. - Marius Meyer; Tobias Kenter; Christian Plessl (J. Parallel Distributed Comput., 2022)

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks. - Marius Meyer; Tobias Kenter; Christian Plessl (ACM Trans. Reconfigurable Technol. Syst., 2023)

Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. - Marius Meyer; Tobias Kenter; Lucian Petrica; Kenneth O'Brien; Michaela Blott; Christian Plessl (Euro-Par (2), 2024)

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. - Abdul Rehman Tareen; Marius Meyer; Christian Plessl; Tobias Kenter (FCCM, 2024)

AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. - Gerrit Pape; Bjarne Wintermann; Linus Jungemann; Michael Lass; Marius Meyer; Heinrich Riebler; Christian Plessl (HEART, 2025)