Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding. - Marjan Karkooti; Joseph R. Cavallaro (ITCC (1), 2004)

Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. - Marjan Karkooti; Predrag Radosavljevic; Joseph R. Cavallaro (ASAP, 2006)

High-throughput multi-rate LDPC decoder based on architecture-oriented parity check matrices. - Predrag Radosavljevic; Alexandre de Baynast; Marjan Karkooti; Joseph R. Cavallaro (EUSIPCO, 2006)

Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area. - Predrag Radosavljevic; Alexandre de Baynast; Marjan Karkooti; Joseph R. Cavallaro (PIMRC, 2006)

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes. - Yang Sun 001; Marjan Karkooti; Joseph R. Cavallaro (ISCAS, 2007)

Cooperative Communications Using Scalable, Medium Block-length LDPC Codes. - Marjan Karkooti; Joseph R. Cavallaro (WCNC, 2008)

Configurable LDPC Decoder Architectures for Regular and Irregular Codes. - Marjan Karkooti; Predrag Radosavljevic; Joseph R. Cavallaro (J. Signal Process. Syst., 2008)