A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback. - Declan Dalton; Kwet Chai; Eric Evans; Mark A. Ferriss; Dave Hitchcox; Paul Murray; Sivanendra Selvanayagam; Paul Shepherd; Lawrence DeVito (IEEE J. Solid State Circuits, 2005)

A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme. - Mark A. Ferriss; Michael P. Flynn (ISSCC, 2007)

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme. - Mark A. Ferriss; Michael P. Flynn (IEEE J. Solid State Circuits, 2008)

A fractional-N PLL modulator with flexible direct digital phase modulation. - Mark A. Ferriss; David T. Lin; Michael P. Flynn (CICC, 2009)

Indirect phase noise sensing for self-healing voltage controlled oscillators. - Soner Yaldiz; Vehbi Calayir; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; José A. Tierno (CICC, 2011)

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Lawrence T. Pileggi; Ramesh Harjani; et al. (CICC, 2012)

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; Aydin Babakhani; Soner Yaldiz; Bodhisatwa Sadhu; Alberto Valdes-Garcia; José A. Tierno; Daniel J. Friedman (VLSIC, 2012)

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (CICC, 2013)

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; José A. Tierno; Aydin Babakhani; Soner Yaldiz; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2013)

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. - Bodhisatwa Sadhu; Mark A. Ferriss; Arun Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pileggi; et al. (IEEE J. Solid State Circuits, 2013)

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Larry T. Pileggi; Ramesh Harjani; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". - Bodhisatwa Sadhu; Mark A. Ferriss; Arun S. Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pillage; et al. (IEEE J. Solid State Circuits, 2013)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

A 28 GHz Hybrid PLL in 32 nm SOI CMOS. - Mark A. Ferriss; Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Daniel J. Friedman (IEEE J. Solid State Circuits, 2014)

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance. - Bodhisatwa Sadhu; Mark A. Ferriss; Alberto Valdes-Garcia (IEEE J. Solid State Circuits, 2015)

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2016)

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. - Bodhisatwa Sadhu; Yahya M. Tousi; Joakim Hallin; Stefan Sahl; Scott K. Reynolds; Orjan Renstrom; Kristoffer Sjogren; Olov Haapalahti; Nadav Mazor; Bo Bokinge; Gustaf Weibull; Håkan Bengtsson; et al. (IEEE J. Solid State Circuits, 2017)

A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation. - Bodhisatwa Sadhu; Arun Paidimarri; Mark A. Ferriss; Mark Yeck; Xiaoxiong Gu; Alberto Valdes-Garcia (mmNets, 2018)

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. - Bodhisatwa Sadhu; Alberto Valdes-Garcia; Jean-Olivier Plouchart; Herschel A. Ainspan; Arpit K. Gupta; Mark A. Ferriss; Mark Yeck; Mihai Sanduleanu; Xiaoxiong Gu; Christian W. Baks; Duixian Liu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2020)