Industrially proving the SPIRIT consortium specifications for design chain integration. - Christopher K. Lennard; Victor Berman; Saverio Fazzari; Mark A. Indovina; Cary Ussery; Marino Strik; John Wilson; Olivier Florent; François Rémond; Pierre Bricaud (DATE Designers' Forum, 2006)

A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects. - Suryanarayanan Subramaniam; Tanmay Shinde; Padmanabh Deshmukh; Md Shahriar Shamim; Mark A. Indovina; Amlan Ganguly (SoCC, 2017)

A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects. - Tanmay Shinde; Suryanarayanan Subramaniam; Padmanabh Deshmukh; M. Meraj Ahmed; Mark A. Indovina; Amlan Ganguly (ACM Great Lakes Symposium on VLSI, 2018)

Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects. - Abhishek Vashist; Amlan Ganguly; Mark A. Indovina (NOCS, 2018)

The IANET Hardware Accelerator for Audio and Visual Data Classification. - Rohini J. Gillela; Amlan Ganguly; Dorin Patru; Mark A. Indovina (SoCC, 2020)

pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning. - Purab Ranjan Sutradhar; Mark Connolly; Sathwika Bavikadi; Sai Manoj Pudukotai Dinakarrao; Mark A. Indovina; Amlan Ganguly (IEEE Comput. Archit. Lett., 2020)

Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory. - Mark Connolly; Purab Ranjan Sutradhar; Mark A. Indovina; Amlan Ganguly (ICCD, 2021)

POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications. - Sathwika Bavikadi; Purab Ranjan Sutradhar; Mark A. Indovina; Amlan Ganguly; Sai Manoj Pudukotai Dinakarrao (DSD, 2022)

Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware. - Prangon Das; Purab Ranjan Sutradhar; Mark A. Indovina; Sai Manoj Pudukotai Dinakarrao; Amlan Ganguly (SOCC, 2022)

Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications. - Purab Ranjan Sutradhar; Sathwika Bavikadi; Mark Connolly; Savankumar Prajapati; Mark A. Indovina; Sai Manoj Pudukotai Dinakarrao; Amlan Ganguly (IEEE Trans. Parallel Distributed Syst., 2022)

FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications. - Purab Ranjan Sutradhar; Sathwika Bavikadi; Mark A. Indovina; Sai Manoj Pudukotai Dinakarrao; Amlan Ganguly (ACM Great Lakes Symposium on VLSI, 2023)

CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs. - Christie Agbalessi; Mark A. Indovina (SOCC, 2023)

3DL-PIM: A Look-Up Table Oriented Programmable Processing in Memory Architecture Based on the 3-D Stacked Memory for Data-Intensive Applications. - Purab Ranjan Sutradhar; Sathwika Bavikadi; Sai Manoj Pudukotai Dinakarrao; Mark A. Indovina; Amlan Ganguly (IEEE Trans. Emerg. Top. Comput., 2024)

ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator. - Sathwika Bavikadi; Purab Ranjan Sutradhar; Mark A. Indovina; Amlan Ganguly; Sai Manoj Pudukotai Dinakarrao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

The State of Simulation Frameworks for Evaluating Emerging LLM Accelerators. - Stefan Maczynski; Amlan Ganguly; Mark A. Indovina (ACM Great Lakes Symposium on VLSI, 2025)

BrIM: A Branching In-Memory Accelerator. - Stefan Maczynski; Amlan Ganguly; Mark A. Indovina; Purab Ranjan Sutradhar; Sai Manoj Pudukotai Dinakarrao; Sathwika Bavikadi (ACM Great Lakes Symposium on VLSI, 2025)