Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. - Fredrick Angelo R. Galapon; Mark Allen D. C. Agaton; Arcel G. Leynes; Lemuel Neil M. Noveno; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Marc D. Rosales; Maria Theresa G. de Leon; Rico Jossel M. Maestro (NGCAS, 2018)

A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications. - Fredrick Angelo R. Galapon; Mark Allen D. C. Agaton; Arcel G. Leynes; Lemuel Neil M. Noveno; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Marc D. Rosales; Maria Theresa G. de Leon; Rico Jossel M. Maestro (TENCON, 2018)

A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process. - Fredrick Angelo R. Galapon; Mark Allen D. C. Agaton; Arcel G. Leynes; Lemuel Neil M. Noveno; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Marc D. Rosales; Maria Theresa G. de Leon; Rico Jossel M. Maestro (J. Low Power Electron., 2019)