Silicon Trends and Limits for Advanced Microprocessors. - Mark Bohr (Commun. ACM, 1998)

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2005)

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2006)

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (ISSCC, 2008)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

The new era of scaling in an SoC world. - Mark Bohr (ISSCC, 2009)

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (ISSCC, 2009)

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (IEEE J. Solid State Circuits, 2009)

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (IEEE J. Solid State Circuits, 2010)

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (ISSCC, 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)