A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. - Chao-Chieh Li; Tsung-Hsien Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Kenny Hsieh; Mark Chen 001; Augusto Ronchini Ximenes; et al. (VLSI Circuits, 2016)

A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. - Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (CICC, 2017)

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. - Chao-Chieh Li; Min-Shueh Yuan; Chih-Hsien Chang; Yu-Tso Lin; Chia-Chun Liao; Kenny Hsieh; Mark Chen 001; Robert Bogdan Staszewski (ISSCC, 2017)

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. - Ting-Kuei Kuan; Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2018)

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. - Feng-Wei Kuo; Masoud Babaie; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Mark Chen 001; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. - Feng-Wei Kuo; Zhirui Zong; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Mark Chen 001; Robert Bogdan Staszewski (ESSCIRC, 2019)

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2019)

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. - Kai Xu; Feng-Wei Kuo; Huan-Neng Ron Chen; Lan-Chou Cho; Chewnpu Jou; Mark Chen 001; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2019)

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. - Mao-Hsuan Chou; Ya-Tin Chang; Tsung-Hsien Tsai; Tsung-Che Lu; Chia-Chun Liao; Hung-Yi Kuo; Ruey-Bin Sheen; Chih-Hsien Chang; Kenny C.-H. Hsieh; Alvin Leng Sun Loke; Mark Chen 001 (VLSI Circuits, 2020)