A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. - James Montanaro; Richard T. Witek; Krishna Anne; Andrew J. Black; Elizabeth M. Cooper; Daniel W. Dobberpuhl; Paul M. Donahue; Jim Eno; Gregory W. Hoeppner; David Kruckemyer; Thomas H. Lee; Peter C. M. Lin; et al. (Digit. Tech. J., 1997)

A low-cost, 300-MHz, RISC CPU with attached media processor. - Sribalan Santhanam; Allen J. Baum; David Bertucci; Mike Braganza; Kevin Broch; Todd Broch; James Burnette; Edward Chang; Kwong-Tak Chui; Dan Dobberpuhl; Paul M. Donahue; Joel Grodstein; et al. (IEEE J. Solid State Circuits, 1998)

A 2× load/store pipe for a low-power 1-GHz embedded processor. - Zongjian Chen; Daniel Murray; Steve Nishimoto; Mark H. Pearce; Max Oyker; Daniel Rodriguez; Robert Rogenmoser; Dongwook (Drew) Suh; Erik Supnet; Vincent von Kaenel; George Yiu (IEEE J. Solid State Circuits, 2003)