Mark A. Heinrich

Orcid: 0000-0002-2843-5503

Affiliations:
  • University of Central Florida, Orlando, USA


According to our database1, Mark A. Heinrich authored at least 31 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Hardware Support for Durable Atomic Instructions for Persistent Parallel Programming.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Persistent Memory Objects: Fast and Easy Crash Consistency for Persistent Memory.
CoRR, 2022

Improving the Security and Programmability of Persistent Memory Objects.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

2020
KnightSim: A Fast Discrete Event-Driven Simulation Methodology for Computer Architectural Simulation.
IEEE Trans. Computers, 2020

2018
Igloos Make the Cold Bearable: A Novel HDD Technology for Cold Storage.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

A Fast Discrete Event Driven Simulation Methodology for Computer Architectural Simulation.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

2017
M2S-CGM: A Detailed Architectural Simulator for Coherent CPU-GPU Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2007
Integrated Memory Controllers with Parallel Coherence Streams.
IEEE Trans. Parallel Distributed Syst., 2007

Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

2004
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols.
IEEE Trans. Parallel Distributed Syst., 2004

The Impact of Negative Acknowledgments in Shared Memory Scientific Applications.
IEEE Trans. Parallel Distributed Syst., 2004

Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.
IEEE Trans. Computers, 2004

SMTp: An Architecture for Next-generation Scalable Multi-threading.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003
Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation.
IEEE Trans. Computers, 2003

Ocean warning: avoid drowning.
SIGARCH Comput. Archit. News, 2003

Active Memory Techniques for ccNUMA Multiprocessors.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Active I/O Switches in System Area Networks.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Cache Coherence Protocol Design for Active Memory Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Leveraging cache coherence in active memory systems.
Proceedings of the 16th international conference on Supercomputing, 2002

2000
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

Using Meta-level Compilation to Check FLASH Protocol Code.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999
A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory.
IEEE Trans. Computers, 1999

Cache-coherent distributed shared memory: perspectives on its development and future challenges.
Proc. IEEE, 1999

The Performance and Scalability of DSM Cache Coherence Protocols.
Proceedings of the Ninth SIAM Conference on Parallel Processing for Scientific Computing, 1999

1998
Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

The Stanford FLASH Multiprocessor.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Digital System Simulation: Methodologies and Examples.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Hardware/software co-design of the Stanford FLASH multiprocessor.
Proc. IEEE, 1997

1996
Integrating Performance Monitoring and Communication in Parallel Computers.
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1996

1994
The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor.
Proceedings of the ASPLOS-VI Proceedings, 1994


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