Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. - Pak K. Chan; Mark J. Boyd; Sezer Gören 001; K. Klenk; V. Kodavati; R. Kundu; M. Margolese; J. Sun; Katsuharu Suzuki; E. Thorne; X. Wang; J. Xu; et al. (FCCM, 1999)

A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems. - Mark J. Boyd; Tracy Larrabee (FCCM, 2000)