Software Accelerated Functional Fault Simulation for Data-Path Architectures. - Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 1995)

Hierarchical Functional-Fault Simulation for High-Level Synthesis. - Mark Kassab; Janusz Rajski; Jerzy Tyszer (ITC, 1995)

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. - Aiman H. El-Maleh; Mark Kassab; Janusz Rajski (DAC, 1998)

Logic BIST for large industrial designs: real issues and case studies. - Graham Hetherington; Tony Fryars; Nagesh Tamarapalli; Mark Kassab; Abu S. M. Hassan; Janusz Rajski (ITC, 1999)

Embedded Deterministic Test for Low-Cost Manufacturing Test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001; Rob Thompson; Kun-Han Tsai; Andre Hertwig; Nagesh Tamarapalli; Grzegorz Mrugalski; Geir Eide; Jun Qian (ITC, 2002)

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. - Frank Poehl; Matthias Beck; Ralf Arnold; Peter Muhmenthaler; Nagesh Tamarapalli; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2003)

Embedded Deterministic Test for Low-Cost Manufacturing. - Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Nagesh Tamarapalli; Jerzy Tyszer; Jun Qian (IEEE Des. Test Comput., 2003)

Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. - Brady Benware; Cam Lu; John Van Slyke; Prabhu Krishnamurthy; Robert Madge; Martin Keim; Mark Kassab; Janusz Rajski (ITC, 2004)

Realizing High Test Quality Goals with Smart Test Resource Usage. - Xinli Gu; Cyndee Wang; Abby Lee; Bill Eklow; Kun-Han Tsai; Jan Arild Tofte; Mark Kassab; Janusz Rajski (ITC, 2004)

Embedded deterministic test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

At-Speed Testing with Timing Exceptions and Constraints-Case Studies. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Takeo Kobayashi; Janusz Rajski; Bruce Swanson; Darryl Walters; Yasuo Sato; Toshiharu Asaka; Takashi Aikyo (ATS, 2006)

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. - Xijiang Lin; Kun-Han Tsai; Chen Wang 014; Mark Kassab; Janusz Rajski; Takeo Kobayashi; Randy Klingenberg; Yasuo Sato; Shuji Hamada; Takashi Aikyo (ATS, 2006)

OCI: Open Compression Interface. - Bruce Cory; Rohit Kapur; Mick Tegethoff; Mark Kassab; Brion L. Keller; Kee Sup Kim; Dwayne Burek; Steven F. Oakland; Benoit Nadeau-Dostie (ITC, 2006)

X-Press Compactor for 1000x Reduction of Test Data. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2006)

Test Generation for Timing-Critical Transition Faults. - Xijiang Lin; Mark Kassab; Janusz Rajski (ATS, 2007)

Test Generation in the Presence of Timing Exceptions and Constraints. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Janusz Rajski (DAC, 2007)

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. - Jerzy Tyszer; Janusz Rajski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Mark Kassab; Wu-Tung Cheng; Manish Sharma; Liyang Lai (IEEE Des. Test Comput., 2007)

Low Power Scan Shift and Capture in the EDT Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Test Generation for Designs with On-Chip Clock Generators. - Xijiang Lin; Mark Kassab (Asian Test Symposium, 2009)

Low-Power Scan Operation in Test Compression Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Dynamic channel allocation for higher EDT compression in SoC designs. - Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ITC, 2010)

Low capture power at-speed test in EDT environment. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Xijiang Lin; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2010)

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. - Tom Waayers; Richard Morren; Xijiang Lin; Mark Kassab (ITC, 2010)

At-speed scan test with low switching activity. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Mark Kassab (VTS, 2010)

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. - Jakub Janicki; Jerzy Tyszer; Avijit Dutta; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2011)

A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. - Manish Sharma; Avijit Dutta; Wu-Tung Cheng; Brady Benware; Mark Kassab (ITC, 2011)

EDT Bandwidth Management in SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

Test Time Reduction in EDT Bandwidth Management for SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Timing-Aware ATPG. - Mark Kassab; Benoit Nadeau-Dostie; Xijiang Lin (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Using dynamic shift to reduce test data volume in high-compression designs. - Xijiang Lin; Mark Kassab; Janusz Rajski (ETS, 2014)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

Test Compression Improvement with EDT Channel Sharing in SoC Designs. - Yu Huang 005; Mark Kassab; Jay Jahangiri; Janusz Rajski; Wu-Tung Cheng; Dongkwan Han; Jihye Kim 002; Kun Young Chung (NATW, 2014)

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Hybrid Hierarchical and Modular Tests for SoC Designs. - Guoliang Li 004; Jun Qian; Qinfu Yang; Yuan Zuo; Rui Li 084; Yu Huang 005; Mark Kassab; Janusz Rajski (NATW, 2015)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

TEA: A Test Generation Algorithm for Designs with Timing Exceptions. - Naixing Wang; Chen Wang 014; Kun-Han Tsai; Wu-Tung Cheng; Xijiang Lin; Mark Kassab; Irith Pomeranz (ATS, 2019)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski (ETS, 2020)

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Shi-Xuan Zheng (ITC-Asia, 2020)

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. - Jean-François Côté; Mark Kassab; Wojciech Janiszewski; Ricardo Rodrigues 008; Reinhard Meier; Bartosz Kaczmarek; Peter Orlando; Geir Eide; Janusz Rajski; Glenn Colón-Bonet; Naveen Mysore; Ya Yin; et al. (ITC, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

Effective Design of Layout-Friendly EDT Decompressor. - Yu Huang 005; Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Jeffrey Mayer (VTS, 2020)

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. - Shi-Xuan Zheng; Chung-Yu Yeh; Kuen-Jong Lee; Chen Wang 014; Wu-Tung Cheng; Mark Kassab; Janusz Rajski; Sudhakar M. Reddy (VTS, 2022)

Efficient Test Compression Configuration Selection. - Chong-Siao Ye; Shi-Xuan Zheng; Fong-Jyun Tsai; Chen Wang 014; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Justyna Zawada; Mark Kassab; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)