Routing Strategies for High Speed Parallel Data Compression. - Mark Milward; José Luis Núñez; David J. Mulvaney (PDPTA, 2003)

Design and Implementation of a Lossless Parallel High-Speed Data Compression System. - Mark Milward; José Luis Núñez; David J. Mulvaney (IEEE Trans. Parallel Distributed Syst., 2004)

Automatic synthesis and scheduling of multirate DSP algorithms. - Ying Yi; Mark Milward; Sami Khawam; Ioannis Nousias; Tughrul Arslan (ASP-DAC, 2005)

System-level scheduling on instruction cell based reconfigurable systems. - Ying Yi; Ioannis Nousias; Mark Milward; Sami Khawam; Tughrul Arslan; Iain Lindsay (DATE, 2006)

H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture. - Adam Major; Ying Yi; Ioannis Nousias; Mark Milward; Sami Khawam; Tughrul Arslan (SoCC, 2006)

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. - Adam Major; Ioannis Nousias; Sami Khawam; Mark Milward; Ying Yi; Tughrul Arslan (AHS, 2007)

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays. - Ioannis Nousias; Sami Khawam; Mark Milward; Mark Muir; Tughrul Arslan (AHS, 2007)

Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems. - Nazish Aslam; Mark Milward; Ioannis Nousias; Tughrul Arslan; Ahmet T. Erdogan (FCCM, 2007)

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. - Adam Major; Ioannis Nousias; Sami Khawam; Mark Milward; Ying Yi; Mark Muir; Tughrul Arslan (FPL, 2007)

A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays. - Ioannis Nousias; Sami Khawam; Mark Milward; Mark Muir; Tughrul Arslan (FPL, 2007)

Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems. - Nazish Aslam; Mark Milward; Ioannis Nousias; Tughrul Arslan; Ahmet T. Erdogan (IPDPS, 2007)

Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture. - Zahid Khan; Tughrul Arslan; Ahmet T. Erdogan; Sami Khawam; Ioannis Nousias; Mark Milward; Ying Yi (SoCC, 2007)

Extensible software emulator for reconfigurable instruction cell based processors. - Mark Muir; Iain Lindsay; Tughrul Arslan; Ioannis Nousias; Sami Khawam; Mark Milward; Nazish Aslam; Adam Major (SoCC, 2008)

Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures. - Nazish Aslam; Mark Milward; Ahmet T. Erdogan; Tughrul Arslan (IEEE Trans. Very Large Scale Integr. Syst., 2008)

The Reconfigurable Instruction Cell Array. - Sami Khawam; Ioannis Nousias; Mark Milward; Ying Yi; Mark Muir; Tughrul Arslan (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Embedded UML design flow to the configurable LE1 MultiCore VLIW processor. - Mark Milward; David Stevens; Vassilios A. Chouliaras (ReCoSoC, 2012)

Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads. - Vassilios A. Chouliaras; Konstantia Koutsomyti; Simon Parr; David J. Mulvaney; Mark Milward (Microprocess. Microsystems, 2013)