Mark Mohammad Tehranipoor

According to our database1, Mark Mohammad Tehranipoor authored at least 280 papers between 2005 and 2019.

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Bibliography

2019
Probing Assessment Framework and Evaluation of Antiprobing Solutions.
IEEE Trans. VLSI Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Electronics Supply Chain Integrity Enabled by Blockchain.
ACM Trans. Design Autom. Electr. Syst., 2019

Emerging Attacks and Solutions for Secure Hardware in the Internet of Things.
IEEE Trans. Dependable Sec. Comput., 2019

Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes.
IACR Cryptology ePrint Archive, 2019

Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
IACR Cryptology ePrint Archive, 2019

Theoretical and Practical Approaches for Hardness Amplification of PUFs.
IACR Cryptology ePrint Archive, 2019

Upgrade/Downgrade: Efficient and Secure Legacy Electronic System Replacement.
IEEE Design & Test, 2019

Defense-in-Depth: A Recipe for Logic Locking to Prevail.
CoRR, 2019

EOP: An Encryption-Obfuscation Solution for Protecting PCBs Against Tampering and Reverse Engineering.
CoRR, 2019

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.
CoRR, 2019

Unlock Your Heart: Next Generation Biometric in Resource-Constrained Healthcare Systems and IoT.
IEEE Access, 2019

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

LPN-based Device Authentication Using Resistive Memory.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

RAM-Jam: Remote Temperature and Voltage Fault Attack on FPGAs using Memory Collisions.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019

A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies.
IEEE Trans. VLSI Syst., 2018

Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs.
IEEE Trans. VLSI Syst., 2018

SCARe: An SRAM-Based Countermeasure Against IC Recycling.
IEEE Trans. VLSI Syst., 2018

Hardware-Enabled Pharmaceutical Supply Chain Security.
ACM Trans. Design Autom. Electr. Syst., 2018

ReSC: An RFID-Enabled Solution for Defending IoT Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2018

UCR: An Unclonable Environmentally Sensitive Chipless RFID Tag For Protecting Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2018

Secure Scan and Test Using Obfuscation Throughout Supply Chain.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

System-on-Chip Platform Security Assurance: Architecture and Validation.
Proceedings of the IEEE, 2018

Detecting Hardware Trojans Inserted by Untrusted Foundry Using Physical Inspection and Advanced Image Processing.
J. Hardware and Systems Security, 2018

Development and Evaluation of Hardware Obfuscation Benchmarks.
J. Hardware and Systems Security, 2018

Challenges and Opportunities in Analog and Mixed Signal (AMS) Integrated Circuit (IC) Security.
J. Hardware and Systems Security, 2018

LDPUF: Exploiting DRAM Latency Variations to Generate Robust Device Signatures.
CoRR, 2018

Secure and Reliable Biometric Access Control for Resource-Constrained Systems and IoT.
CoRR, 2018

Hardware Trojan Detection through Information Flow Security Verification.
CoRR, 2018

Physical Inspection & Attacks: New Frontier in Hardware Security.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs.
Proceedings of the IEEE International Test Conference, 2018

Robust Timing Attack Countermeasure on Virtual Hardware.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Hardware virtualization for protection against power analysis attack.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Robust, low-cost, and accurate detection of recycled ICs using digital signatures.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Device attestation: Past, present, and future.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Power-based side-channel instruction-level disassembler.
Proceedings of the 55th Annual Design Automation Conference, 2018

CIPA: Concurrent IC and PCB Authentication Using On-chip Ring Oscillator Array.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Comprehensive Analysis on Vulnerability of Active Shields to Tilted Microprobing Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Poly-Si-Based Physical Unclonable Functions.
IEEE Trans. VLSI Syst., 2017

Design of Reliable SoCs With BIST Hardware and Machine Learning.
IEEE Trans. VLSI Syst., 2017

Security Beyond CMOS: Fundamentals, Applications, and Roadmap.
IEEE Trans. VLSI Syst., 2017

Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability, and Authentication in the IoT Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2017

Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering.
ACM Trans. Design Autom. Electr. Syst., 2017

Introduction to Cyber-Physical System Security: A Cross-Layer Perspective.
IEEE Trans. Multi-Scale Computing Systems, 2017

SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware.
IEEE Trans. Dependable Sec. Comput., 2017

TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Highly Reliable Key Generation From Electrocardiogram (ECG).
IEEE Trans. Biomed. Engineering, 2017

Benchmarking of Hardware Trojans and Maliciously Affected Circuits.
J. Hardware and Systems Security, 2017

Systematic Correlation and Cell Neighborhood Analysis of SRAM PUF for Robust and Unique Key Generation.
J. Hardware and Systems Security, 2017

Editorial for the Introductory Issue of the Journal of Hardware and Systems Security (HaSS).
J. Hardware and Systems Security, 2017

TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era.
J. Hardware and Systems Security, 2017

Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks.
IACR Cryptology ePrint Archive, 2017

An Access Mechanism for Embedded Sensors in Modern SoCs.
J. Electronic Testing, 2017

Probing Attacks on Integrated Circuits: Challenges and Research Opportunities.
IEEE Design & Test, 2017

Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Aging resilient RO PUF with increased reliability in FPGA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

iPUF: Interconnect PUF with Self-Masking Circuit for Performance Enhancement.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Hardware-Assisted Cybersecurity for IoT Devices.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Hardware trojan detection through information flow security verification.
Proceedings of the IEEE International Test Conference, 2017

Design of a digital IP for 3D-IC die-to-die clock synchronization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Human recognition from photoplethysmography (PPG) based on non-fiducial features.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

A stochastic all-digital weak physically unclonable function for analog/mixed-signal applications.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Comparative Analysis of Hardware Obfuscation for IP Protection.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

FFD: A Framework for Fake Flash Detection.
Proceedings of the 54th Annual Design Automation Conference, 2017

Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017

Standardizing Bad Cryptographic Practice: A Teardown of the IEEE Standard for Protecting Electronic-design Intellectual Property.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, CCS 2017, Dallas, TX, USA, October 30, 2017

ASHES 2017: Workshop on Attacks and Solutions in Hardware Security.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, CCS 2017, Dallas, TX, USA, October 30, 2017

Non-fiducial PPG-based authentication for healthcare application.
Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017

MUTARCH: Architectural diversity for FPGA device and IP security.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A split manufacturing approach for unclonable chipless RFIDs for pharmaceutical supply chain security.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

DOST: Dynamically obfuscated wrapper for split test against IC piracy.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

MPA: Model-assisted PCB attestation via board-level RO and temperature compensation.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits.
IEEE Trans. VLSI Syst., 2016

Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs.
IEEE Trans. VLSI Syst., 2016

Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling.
IEEE Trans. VLSI Syst., 2016

Hardware Trojans: Lessons Learned after One Decade of Research.
ACM Trans. Design Autom. Electr. Syst., 2016

FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs.
ACM Trans. Design Autom. Electr. Syst., 2016

Security and Vulnerability Implications of 3D ICs.
IEEE Trans. Multi-Scale Computing Systems, 2016

Guest Editorial: Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing.
IEEE Trans. Multi-Scale Computing Systems, 2016

Vulnerability Analysis of a Circuit Layout to Hardware Trojan Insertion.
IEEE Trans. Information Forensics and Security, 2016

An Aging-Resistant RO-PUF for Reliable Key Generation.
IEEE Trans. Emerging Topics Comput., 2016

A Survey on Chip to System Reverse Engineering.
JETC, 2016

Hardware Security (Dagstuhl Seminar 16202).
Dagstuhl Reports, 2016

Security Rule Checking in IC Design.
IEEE Computer, 2016

Security validation in IoT space.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test-point insertion efficiency analysis for LBIST applications.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

New Directions in Hardware Security.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Robust bitstream protection in FPGA-based systems through low-overhead obfuscation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Technical demonstration session: Software toolflow for FPGA bitstream obfuscation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.
Proceedings of the 2016 IEEE International Test Conference, 2016

Recycled FPGA detection using exhaustive LUT path delay characterization.
Proceedings of the 2016 IEEE International Test Conference, 2016

Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

AES design improvement towards information safety.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Gate-level netlist reverse engineering for hardware security: Control logic register identification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Hardware security meets biometrics for the age of IoT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

UCR: An unclonable chipless RFID tag.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

A layout-driven framework to assess vulnerability of ICs to microprobing attacks.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Aging attacks for key extraction on permutation-based obfuscation.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

A zero-cost approach to detect recycled SoC chips using embedded SRAM.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Tracking Data Flow at Gate-Level through Structural Checking.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Detecting Hardware Trojans using On-chip Sensors in an ASIC Design.
J. Electronic Testing, 2015

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

ReSC: RFID-Enabled Supply Chain Management and Traceability for Network Devices.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015

Harnessing Nanoscale Device Properties for Hardware Security.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

LBIST pattern reduction by learning ATPG test cube properties.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Performance optimization for on-chip sensors to detect recycled ICs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A pair selection algorithm for robust RO-PUF against environmental variations and aging.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Protecting Endpoint Devices in IoT Supply Chain.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Efficient and secure split manufacturing via obfuscated built-in self-authentication.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Speed Binning Using Machine Learning And On-chip Slack Sensors.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Predictive LBIST model and partial ATPG for seed extraction.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Chip-level anti-reverse engineering using transformable interconnects.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Investigation of obfuscation-based anti-reverse engineering for printed circuit boards.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs.
IEEE Trans. VLSI Syst., 2014

Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits.
IEEE Trans. VLSI Syst., 2014

A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.
Proceedings of the IEEE, 2014

Critical-reliability path identification and delay analysis.
JETC, 2014

Guest Editorial.
IET Computers & Digital Techniques, 2014

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
IEICE Transactions, 2014

A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment.
J. Electronic Testing, 2014

Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead.
J. Electronic Testing, 2014

Cybersecurity Standards: Managing Risk and Creating Resilience.
IEEE Computer, 2014

Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICs.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

T1A: Opportunities and challenges for secure hardware and verifying trust in integrated circuits.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

CSST: An Efficient Secure Split-Test for Preventing IC Piracy.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Bit selection algorithm suitable for high-volume production of SRAM-PUF.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Aging analysis for recycled FPGA detection.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

ARO-PUF: An aging-resistant ring oscillator PUF design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hacking and protecting IC hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

TI-TRNG: Technology Independent True Random Number Generator.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Low-cost On-Chip Structures for Combating Die and IC Recycling.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Advanced Analysis of Cell Stability for Reliable SRAM PUFs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects.
IEEE Trans. VLSI Syst., 2013

Power-safe application of tdf patterns to flip-chip designs during wafer test.
ACM Trans. Design Autom. Electr. Syst., 2013

Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis.
JETC, 2013

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.
J. Electronic Testing, 2013

A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay.
IEEE Design & Test, 2013

A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection.
IEEE Design & Test, 2013

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.
IEEE Design & Test, 2013

A study on the effectiveness of Trojan detection techniques using a red team blue team approach.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Special session 12A: Hot topic counterfeit IC identification: How can test help?
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Anti-counterfeit Techniques: From Design to Resign.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

A novel flow for reducing clock skew considering NBTI effect and process variations.
Proceedings of the International Symposium on Quality Electronic Design, 2013

On design vulnerability analysis and trust benchmarks development.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Functional Fmax test-time reduction using novel DFTs for circuit initialization.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

BISA: Built-in self-authentication for preventing hardware Trojan insertion.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Secure Split-Test for preventing IC piracy by untrusted foundry and assembly.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
Proceedings of the 22nd Asian Test Symposium, 2013

Critical Paths Selection and Test Cost Reduction Considering Process Variations.
Proceedings of the 22nd Asian Test Symposium, 2013

Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements.
IEEE Trans. VLSI Syst., 2012

A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.
IEEE Trans. VLSI Syst., 2012

Layout-Aware Switching Activity Localization to Enhance Hardware Trojan Detection.
IEEE Trans. Information Forensics and Security, 2012

Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits.
J. Low Power Electronics, 2012

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.
J. Low Power Electronics, 2012

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk.
J. Electronic Testing, 2012

A novel method for fast identification of peak current during test.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On pinpoint capture power management in at-speed scan test generation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements.
Proceedings of the 2012 IEEE International Test Conference, 2012

Representative Critical Reliability Paths for low-cost and accurate on-chip aging evaluation.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A zero-overhead IC identification technique using clock sweeping and path delay analysis.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Efficient selection and analysis of critical-reliability paths and gates.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Path-delay fingerprinting for identification of recovered ICs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A sensor-assisted self-authentication framework for hardware trojan detection.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Identification of recovered ICs using fingerprints from a light-weight on-chip sensor.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

PowerMAX: Fast Power Analysis during Test.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities.
IEEE Trans. Information Forensics and Security, 2011

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

A Metric to Target Small-Delay Defects in Industrial Circuits.
IEEE Design & Test of Computers, 2011

Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges.
IEEE Computer, 2011

Power-safe test application using an effective gating approach considering current limits.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Special session: Hot topic: Smart silicon.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Special session 5B: Panel How much toggle activity should we be testing with?
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Case Study: Efficient SDD test generation for very large integrated circuits.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Red team: Design of intelligent hardware trojans with known defense schemes.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Case study: Detecting hardware Trojans in third-party digital IP cores.
Proceedings of the HOST 2011, 2011

Peak power identification on power bumps during test application.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Critical Fault-Based Pattern Generation for Screening SDDs.
Proceedings of the 16th European Test Symposium, 2011

RON: An on-chip ring oscillator network for hardware Trojan detection.
Proceedings of the Design, Automation and Test in Europe, 2011

In-field aging measurement and calibration for power-performance optimization.
Proceedings of the 48th Design Automation Conference, 2011

On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Test and Diagnosis for Small-Delay Defects.
Springer, ISBN: 978-1-4419-8296-4, 2011

2010
Hardware Trojan Horses.
Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions.
IEEE Trans. VLSI Syst., 2010

Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electronics, 2010

A Novel IR-Drop Tolerant Transition Delay Fault Test Pattern Generation Procedure.
J. Low Power Electronics, 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.
IEICE Transactions, 2010

A Survey of Hardware Trojan Taxonomy and Detection.
IEEE Design & Test of Computers, 2010

Guest Editors' Introduction: Confronting the Hardware Trustworthiness Problem.
IEEE Design & Test of Computers, 2010

Power Supply Noise: A Survey on Effects and Research.
IEEE Design & Test of Computers, 2010

Trustworthy Hardware: Identifying and Classifying Hardware Trojans.
IEEE Computer, 2010

A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits.
Proceedings of the 2010 IEEE International Workshop on Information Forensics and Security, 2010

A novel hybrid method for SDD pattern grading and selection.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Is test power reduction through X-filling good enough?
Proceedings of the 2011 IEEE International Test Conference, 2010

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG.
Proceedings of the 5th International Design and Test Workshop, 2010

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Full-circuit SPICE simulation based validation of dynamic delay estimation.
Proceedings of the 15th European Test Symposium, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Novel Physical Unclonable Function with process and environmental variations.
Proceedings of the Design, Automation and Test in Europe, 2010

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk.
Proceedings of the Design, Automation and Test in Europe, 2010

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Emulating and diagnosing IR-drop by using dynamic SDF.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A novel architecture for on-chip path delay measurement.
Proceedings of the 2009 IEEE International Test Conference, 2009

New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

2008
Low-Transition Test Pattern Generation for BIST-Based Applications.
IEEE Trans. Computers, 2008

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity.
J. Low Power Electronics, 2008

SCT: A novel approach for testing and configuring nanoscale devices.
JETC, 2008

Defect Tolerance for Nanoscale Crossbar-Based Devices.
IEEE Design & Test of Computers, 2008

Test-Pattern Grading and Pattern Selection for Small-Delay Defects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

LS-TDF: Low-Switching Transition Delay Fault Pattern Generation.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

Power Distribution Failure Analysis Using Transition-Delay Fault Patterns.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths.
Proceedings of the 2008 IEEE International Test Conference, 2008

Path-RO: a novel on-chip critical path delay measurement under process variations.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Power supply signal calibration techniques for improving detection resolution to hardware Trojans.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation.
Proceedings of the Design, Automation and Test in Europe, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A critical-path-aware partial gating approach for test power reduction.
ACM Trans. Design Autom. Electr. Syst., 2007

Securing Designs against Scan-Based Side-Channel Attacks.
IEEE Trans. Dependable Sec. Comput., 2007

Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.
JETC, 2007

Guest Editorial.
J. Electronic Testing, 2007

Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs.
IEEE Design & Test of Computers, 2007

Supply Voltage Noise Aware ATPG for Transition Delay Faults.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.
Proceedings of the 44th Design Automation Conference, 2007

2006
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.
IEEE Design & Test of Computers, 2006

Improving Transition Delay Test Using a Hybrid Method.
IEEE Design & Test of Computers, 2006

SCT: An Approach For Testing and Configuring Nanoscale Devices.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A novel framework for faster-than-at-speed delay test considering IR-drop effects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Test and recovery for fine-grained nanoscale architectures.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Fine-grained island style architecture for molecular electronic devices.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A new hybrid FPGA with nanoscale clusters and CMOS routing.
Proceedings of the 43rd Design Automation Conference, 2006

Timing-based delay test for screening small delay defects.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Nine-coded compression technique for testing embedded cores in SoCs.
IEEE Trans. VLSI Syst., 2005

Pattern Generation and Estimation for Power Supply Noise Analysis.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

At-Speed Transition Fault Testing With Low Speed Scan Enable.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Enhanced launch-off-capture transition fault testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Securing Scan Design Using Lock and Key Technique.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Low Transition LFSR for BIST-Based Applications.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Partial Gating Optimization for Power Reduction During Test Application.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005


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