Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. - Umut Arslan; Mark P. McCartney; Mudit Bhargava; Xin Li 001; Ken Mai; Lawrence T. Pileggi (CICC, 2008)

Low-overhead, digital offset compensated, SRAM sense amplifiers. - Mudit Bhargava; Mark P. McCartney; Alexander Hoefler; Ken Mai (CICC, 2009)

FPGA-Based Solid-State Drive Prototyping Platform. - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Ken Mai (FCCM, 2011)

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Mudit Bhargava; Ken Mai (FPGA, 2011)

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. - Jangwoo Kim; Hyunggyun Yang; Mark P. McCartney; Mudit Bhargava; Ken Mai; Babak Falsafi (PRDC, 2013)

SRAM Reliability Improvement Using ECC and Circuit Techniques. - Mark P. McCartney (2014)

A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. - Cagla Cakir; Andy W. Chen; Y. K. Chong; Sriram Thyagarajan; Mark P. McCartney; Peixuan Tan; Yulin Shi; Mudit Bhargava (VLSI Circuits, 2019)