VLSI with a very low scale investment. - Mark R. Greenstreet; Peter Møller-Nielsen; Jørgen Staunstrup (Integr., 1987)

From High-Level Descriptions to VLSI Circuits. - Jørgen Staunstrup; Mark R. Greenstreet (BIT, 1988)

Bubbles can make self-timed pipelines fast. - Mark R. Greenstreet; Kenneth Steiglitz (J. VLSI Signal Process., 1990)

Using Synchronized Transitions for Simulation and Timing Verification. - Mark R. Greenstreet (Designing Correct Circuits, 1992)

How fast will the flip flop? - Mark R. Greenstreet; Peter Cahoon (ASYNC, 1994)

Automatic Verification of Refinement. - Trevor Wing Sang Lee; Mark R. Greenstreet; Carl-Johan H. Seger (ICCD, 1994)

Implementing a STARI chip. - Mark R. Greenstreet (ICCD, 1995)

Automatic Verification of Asynchronous Circuits. - Trevor Wing Sang Lee; Mark R. Greenstreet; Carl-Johan H. Seger (IEEE Des. Test Comput., 1995)

Verifying Safety Properties of Differential Equations. - Mark R. Greenstreet (CAV, 1996)

Self-Timed Meshes Are Faster Than Synchronous. - Peggy B. K. Pang; Mark R. Greenstreet (ASYNC, 1997)

Verifying a Self-Timed Divider. - Tarik Ono-Tesfaye; Christoph Kern; Mark R. Greenstreet (ASYNC, 1998)

Integrating Projections. - Mark R. Greenstreet; Ian Mitchell 001 (HSCC, 1998)

Real-Time Merging. - Mark R. Greenstreet (ASYNC, 1999)

A Fast, asP*, RGD Arbiter. - Mark R. Greenstreet; Tarik Ono-Tesfaye (ASYNC, 1999)

Reachability Analysis Using Polygonal Projections. - Mark R. Greenstreet; Ian Mitchell 001 (HSCC, 1999)

Formal verification in hardware design: a survey. - Christoph Kern; Mark R. Greenstreet (ACM Trans. Design Autom. Electr. Syst., 1999)

Pragmatic verification for hybrid and real-time designs. - Mark R. Greenstreet (ACC, 2000)

How to Achieve Worst-Case Performance. - Mark R. Greenstreet; Brian de Alwis (ASYNC, 2001)

Temporal Properties of Self-Timed Rings. - Anthony Winstanley; Mark R. Greenstreet (CHARME, 2001)

A light-weight framework for hardware verification. - Christoph Kern; Tarik Ono-Tesfaye; Mark R. Greenstreet (Int. J. Softw. Tools Technol. Transf., 2001)

A Negative-Overhead, Self-Timed Pipeline. - Mark R. Greenstreet; Brian D. Winters (ASYNC, 2002)

An Event Spacing Experiment. - Mark R. Greenstreet; Anthony Winstanley; Aurélien Garivier (ASYNC, 2002)

Efficient Self-Timed Interfaces for Crossing Clock Domains. - Ajanta Chakraborty; Mark R. Greenstreet (ASYNC, 2003)

Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. - Jihong Ren; Mark R. Greenstreet (DAC, 2003)

Equalizing Filter Design for Crosstalk Cancellation. - Jihong Ren; Mark R. Greenstreet (ISVLSI, 2003)

Surfing: a robust form of wave pipelining using self-timed circuit techniques. - Brian D. Winters; Mark R. Greenstreet (Microprocess. Microsystems, 2003)

A Signal Integrity Test Bed for PCB Buses. - Jihong Ren; Mark R. Greenstreet (ICCD, 2004)

Crosstalk Cancellation for Realistic PCB Buses. - Jihong Ren; Mark R. Greenstreet (PATMOS, 2004)

Energy Efficient Surfing. - Suwen Yang; Brian D. Winters; Mark R. Greenstreet (ASYNC, 2005)

A unified optimization framework for equalization filter synthesis. - Jihong Ren; Mark R. Greenstreet (DAC, 2005)

Noise margin analysis for dynamic logic circuits. - Suwen Yang; Mark R. Greenstreet (ICCAD, 2005)

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. - Bradley R. Quinton; Mark R. Greenstreet; Steven J. E. Wilton (ICCD, 2005)

Analysing the Robustness of Surfing Circuits. - Suwen Yang; Mark R. Greenstreet (FAC, 2005)

Surfing Interconnect. - Mark R. Greenstreet; Jihong Ren (ASYNC, 2006)

System-on-Chip: Reuse and Integration. - Resve A. Saleh; Steven J. E. Wilton; Shahriar Mirabbasi; Alan J. Hu; Mark R. Greenstreet; Guy Lemieux; Partha Pratim Pande; Cristian Grecu; André Ivanov (Proc. IEEE, 2006)

A Jitter Attenuating Timing Chain. - Suwen Yang; Mark R. Greenstreet; Jihong Ren (ASYNC, 2007)

Simulating Improbable Events. - Suwen Yang; Mark R. Greenstreet (DAC, 2007)

Computing synchronizer failure probabilities. - Suwen Yang; Mark R. Greenstreet (DATE, 2007)

Circuit Level Verification of a High-Speed Toggle. - Chao Yan 001; Mark R. Greenstreet (FMCAD, 2007)

A Survey and Taxonomy of GALS Design Styles. - Paul Teehan; Mark R. Greenstreet; Guy G. Lemieux (IEEE Des. Test Comput., 2007)

Surfing Pipelines: Theory and Implementation. - Suwen Yang; Brian D. Winters; Mark R. Greenstreet (IEEE J. Solid State Circuits, 2007)

An efficient linear programming solver for optimal filter synthesis. - Jihong Ren; Chen Greif; Mark R. Greenstreet (Numer. Linear Algebra Appl., 2007)

Faster projection based methods for circuit level verification. - Chao Yan 001; Mark R. Greenstreet (ASP-DAC, 2008)

Verifying an Arbiter Circuit. - Chao Yan 001; Mark R. Greenstreet (FMCAD, 2008)

Verifying start-up conditions for a ring oscillator. - Mark R. Greenstreet; Suwen Yang (ACM Great Lakes Symposium on VLSI, 2008)

Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds. - Brad D. Bingham; Mark R. Greenstreet (ISPA, 2008)

Energy Optimal Scheduling on Multiprocessors with Migration. - Brad D. Bingham; Mark R. Greenstreet (ISPA, 2008)

Practical Asynchronous Interconnect Network Design. - Bradley R. Quinton; Mark R. Greenstreet; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Synchronizer Behavior and Analysis. - Ian W. Jones; Suwen Yang; Mark R. Greenstreet (ASYNC, 2009)

Verifying VLSI Circuits. - Mark R. Greenstreet (ATVA, 2009)

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. - Paul Teehan; Guy G. Lemieux; Mark R. Greenstreet (FPGA, 2009)

A modular synchronizing FIFO for NoCs. - Tarik Ono-Tesfaye; Mark R. Greenstreet (NOCS, 2009)

Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. - Paul Teehan; Guy G. Lemieux; Mark R. Greenstreet (NOCS, 2009)

Formal Verification of an Arbiter Circuit. - Chao Yan 001; Mark R. Greenstreet; Jochen Eisinger (ASYNC, 2010)

Varactor-based signal restoration for near-speed-of-light surfing global interconnect. - Suwen Yang; Robert J. Drost; Mark R. Greenstreet; Shahriar Mirabbasi; Frank O'Mahony (CICC, 2010)

Synchronizer Performance in Deep Sub-Micron Technology. - Suwen Yang; Ian W. Jones; Mark R. Greenstreet (ASYNC, 2011)

Parameterized verification of deadlock freedom in symmetric cache coherence protocols. - Brad D. Bingham; Mark R. Greenstreet; Jesse D. Bingham (FMCAD, 2011)

On the Energy Complexity of Parallel Algorithms. - Vijay Anand Korthikanti; Gul Agha; Mark R. Greenstreet (ICPP, 2011)

Oscillator verification with probability one. - Chao Yan 001; Mark R. Greenstreet (FMCAD, 2012)

Modeling Energy-Time Trade-Offs in VLSI Computation. - Brad D. Bingham; Mark R. Greenstreet (IEEE Trans. Computers, 2012)

Distributed Explicit State Model Checking of Deadlock Freedom. - Brad D. Bingham; Jesse D. Bingham; John Erickson; Mark R. Greenstreet (CAV, 2013)

Verifying global convergence for a digital phase-locked loop. - Jijie Wei; Yan Peng; Ge Yu; Mark R. Greenstreet (FMCAD, 2013)

Response property checking via distributed state space exploration. - Brad D. Bingham; Mark R. Greenstreet (FMCAD, 2014)

Verifying global start-up for a Möbius ring-oscillator. - Chao Yan 001; Mark R. Greenstreet; Suwen Yang (Formal Methods Syst. Des., 2014)

Integrating SMT with Theorem Proving for Analog/Mixed-Signal Circuit Verification. - Yan Peng; Mark R. Greenstreet (NFM, 2015)

Extending ACL2 with SMT Solvers. - Yan Peng; Mark R. Greenstreet (ACL2, 2015)

Finding Glitches Using Formal Methods. - Yan Peng; Ian W. Jones; Mark R. Greenstreet (ASYNC, 2016)

Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs. - Ameer M. S. Abdelhadi; Mark R. Greenstreet (ASYNC, 2017)

Explaining Metastability in Real Synchronizers. - Justin Reiher; Mark R. Greenstreet; Ian W. Jones (ASYNC, 2018)

Real Vector Spaces and the Cauchy-Schwarz Inequality in ACL2(r). - Carl Kwan; Mark R. Greenstreet (ACL2, 2018)

Convex Functions in ACL2(r). - Carl Kwan; Mark R. Greenstreet (ACL2, 2018)

Smtlink 2.0. - Yan Peng; Mark R. Greenstreet (ACL2, 2018)

Verifying Timed, Asynchronous Circuits using ACL2. - Yan Peng; Mark R. Greenstreet (ASYNC, 2019)

Finding All DC Operating Points Using Interval Arithmetic Based Verification Algorithms. - Itrat A. Akhter; Justin Reiher; Mark R. Greenstreet (DATE, 2019)

Integrating SMT with Theorem Proving for Verification of Analog and Mixed-Signal Circuits (Invited Tutorial). - Mark R. Greenstreet (FMCAD, 2019)

Optimization and Comparison of Synchronizers. - Justin Reiher; Mark R. Greenstreet (ASYNC, 2020)

Shellac: A Compiler Synthesizer for Concurrent Programs. - Christopher K. Chen; Margo I. Seltzer; Mark R. Greenstreet (VSTTE, 2022)