A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. - Ho-Young Lee; Tae-Hwan Oh; Ho-Jin Park; Hae-Seung Lee; Mark Spaeth; Jae-Whui Kim (CICC, 2007)

A 32-core RISC microprocessor with network accelerators, power management and testability features. - Brian Miller; Derek Brasili; Tim Kiszely; Rob Kuhn; Rahul Mehrotra; Manan Salvi; Mandar Kulkarni; Anand Varadharajan; Shi-Huang Yin; William Lin; Adam Hughes; Bill Stysiack; et al. (ISSCC, 2012)