Timing Characterization of Dual-edge Triggered Flip-flops. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ICCD, 2001)

Conditional techniques for low power consumption flip-flops. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ICECS, 2001)

Comparative analysis of double-edge versus single-edge triggered clocked storage elements. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ISCAS (5), 2002)

Conditional pre-charge techniques for power-efficient dual-edge clocking. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ISLPED, 2002)

A novel cost effective demosaicing approach. - Rastislav Lukac; Konstantinos N. Plataniotis; Dimitrios Hatzinakos; Marko Aleksic (IEEE Trans. Consumer Electron., 2004)

Coding for the blackwell channel: a survey propagation approach. - Wei Yu 001; Marko Aleksic (ISIT, 2005)

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. - Marko Aleksic; Nikola Nedovic; K. Wayne Current; Vojin G. Oklobdzija (PATMOS, 2005)

A new CFA interpolation framework. - Rastislav Lukac; Konstantinos N. Plataniotis; Dimitrios Hatzinakos; Marko Aleksic (Signal Process., 2006)

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. - Marko Aleksic; Nikola Nedovic; K. Wayne Current; Vojin G. Oklobdzija (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. - Haechang Lee; Kun-Yung Ken Chang; Jung-Hoon Chun; Ting Wu 003; Yohan Frans; Brian S. Leibowitz; Nhat Nguyen; T. J. Chin; Kambiz Kaviani; Jie Shen 010; Xudong Shi 004; Wendemagegnehu T. Beyene; et al. (IEEE J. Solid State Circuits, 2009)

Capacity of a Class of Modulo-Sum Relay Channels. - Marko Aleksic; Peyman Razaghi; Wei Yu 001 (IEEE Trans. Inf. Theory, 2009)

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. - Brian S. Leibowitz; Robert Palmer; John Poulton; Yohan Frans; Simon Li; John M. Wilson 002; Michael Bucher; Andrew M. Fuller; John G. Eyles; Marko Aleksic; Trey Greer; Nhat Nguyen (IEEE J. Solid State Circuits, 2010)

A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS. - Marko Aleksic (ESSCIRC, 2014)

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. - Reza Navid; E-Hung Chen; Masum Hossain; Brian S. Leibowitz; Jihong Ren; Chuen-Huei Adam Chou; Barry Daly; Marko Aleksic; Bruce Su; Simon Li; Makarand Shirasgaonkar; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2015)

Non-physical Painting Restoration in Improved Reality. - Marko Aleksic; Vanja Jovanovic (VRTCH, 2018)