Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools. - Markus Fritscher; Johannes Knödtel; Marc Reichenbach; Dietmar Fey (ICECS, 2019)

A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. - Johannes Knödtel; Markus Fritscher; Daniel Reiser; Dietmar Fey; Marco Breiling; Marc Reichenbach (MOCAST, 2020)

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. - Markus Fritscher; Johannes Knödtel; Daniel Reiser; Maen Mallah; Stefan Pechmann; Dietmar Fey; Marc Reichenbach (LASCAS, 2021)

Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks. - Markus Fritscher; Johannes Knödtel; Maen Mallah; Stefan Pechmann; Emilio Pérez-Bosch Quesada; Tommaso Rizzi; Christian Wenger; Marc Reichenbach (SAMOS, 2021)

Accelerating Veins Simulations by Utilizing Task Parallelism on a HPC Cluster without Introducing Major Inaccuracies. - Markus Fritscher; Gabriel Dengler; Cord Bleibaum; Michael Niebisch; Reinhard German (CSNDSP, 2022)

Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations. - Daniel Reiser; Marc Reichenbach; Tommaso Rizzi; Andrea Baroni; Markus Fritscher; Christian Wenger; Cristian Zambelli; Davide Bertozzi (NEWCAS, 2023)

One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing. - Max Uhlmann; Emilio Pérez-Bosch Quesada; Markus Fritscher; Eduardo Pérez; Markus Andreas Schubert; Marc Reichenbach; Philip Ostrovskyy; Christian Wenger; Gerhard Kahmen (NEWCAS, 2023)

Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins. - Markus Fritscher; Alessandro Veronesi; Andrea Baroni; Jianan Wen; Thorsten Spätling; Mamathamba Kalishettyhalli Mahadevaiah; Norbert Herfurth; Eduardo Pérez; Markus Ulbricht 002; Marc Reichenbach; Amelie Hagelauer; Milos Krstic (ISC Workshops, 2023)

An RRAM-based building block for reprogrammable non-uniform sampling ADCs. - Abhinav Vishwakarma; Markus Fritscher; Amelie Hagelauer; Marc Reichenbach (it Inf. Technol., 2023)

Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level. - Johannes Kliemt; Markus Fritscher; Dietmar Fey (ARCS, 2024)

Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator. - Jianan Wen; Andrea Baroni; Eduardo Pérez; Max Uhlmann; Markus Fritscher; Karthik KrishneGowda; Markus Ulbricht 002; Christian Wenger; Milos Krstic (DATE, 2024)

Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks. - Ruolan Jia; Stefan Pechmann; Markus Fritscher; Christian Wenger; Lei Zhang; Amelie Hagelauer (DCIS, 2024)

Hardware-Friendly Nyström Approximation for Water Treatment Anomaly Detection. - Marcin Aftowicz; Markus Fritscher; Kai Lehniger; Christian Wenger; Peter Langendörfer; Marcin Brzozowski (IECON, 2024)

Area-Efficient Digital Design Using RRAM-CMOS Standard Cells. - Markus Fritscher; Max Uhlmann; Philip Ostrovskyy; Daniel Reiser; Junchao Chen 001; Markus Andreas Schubert; Carsten Schulze; Gerhard Kahmen; Dietmar Fey; Marc Reichenbach; Milos Krstic; Christian Wenger (ISVLSI, 2024)

From Device to Application - Integrating RRAM Accelerator Blocks into Large AI Systems. - Markus Fritscher; Christian Wenger; Milos Krstic (ISVLSI, 2024)

Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment. - Jianan Wen; Fabian Luis Vargas 001; Fukun Zhu; Daniel Reiser; Andrea Baroni; Markus Fritscher; Eduardo Pérez; Marc Reichenbach; Christian Wenger; Milos Krstic (LATS, 2024)

Dependable Neuromorphic Computing-in-Memory Architectures. - Farhad Merchant; Ankit Bende; Markus Fritscher; Shahar Kvatinsky; Simranjeet Singh; Vikas Rana; Regina Dittmann; Keerthi Dorai Swamy Reddy; Christian Wenger; Fouwad Jamil Mir; Mottaqiallah Taouil; Manil Dev Gomony; et al. (ETS, 2025)

RISC-V CPU Design Using RRAM-CMOS Standard Cells. - Markus Fritscher; Max Uhlmann; Philip Ostrovskyy; Daniel Reiser; Junchao Chen 001; Jianan Wen; Carsten Schulze; Gerhard Kahmen; Dietmar Fey; Marc Reichenbach; Milos Krstic; Christian Wenger (IEEE Trans. Very Large Scale Integr. Syst., 2025)