On-chip digital noise reduction for integrated CMOS Cameras. - Markus Rullmann; Jens-Uwe Schluessler; René Schüffny (VCIP, 2003)

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. - Markus Rullmann; Sebastian Siegel; Renate Merker (IPDPS, 2005)

Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. - Markus Rullmann; Renate Merker (ARCS Workshops, 2006)

Maximum edge matching for reconfigurable computing. - Markus Rullmann; Renate Merker (IPDPS, 2006)

A Reconfiguration Aware Circuit Mapper for FPGAs. - Markus Rullmann; Renate Merker (IPDPS, 2007)

Fine grain reconfigurable architectures. - Josef Angermeier; Mateusz Majer; Jürgen Teich; Lars Braun; Tobias Schwalb; Philipp Graf; Michael Hübner 001; Jürgen Becker 001; Enno Lübbers; Marco Platzner; Christopher Claus; Walter Stechele; et al. (FPL, 2008)

Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. - Markus Rullmann; Renate Merker (FPT, 2008)

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. - Markus Rullmann; Renate Merker; Heiko Hinkelmann; Peter Zipf; Manfred Glesner (FPL, 2009)

Design Methods and Tools for Improved Partial Dynamic Reconfiguration. - Markus Rullmann; Renate Merker (Dynamically Reconfigurable Systems, 2010)

A Cost Model for Partial Dynamic Reconfiguration. - Markus Rullmann; Renate Merker (Trans. High Perform. Embed. Archit. Compil., 2011)