Synthesis of intermediate memories for the data supply to processor arrays. - Mirjam Schönfeld; Markus Schwiegershausen; Peter Pirsch (Algorithms and Parallel VLSI Architectures, 1991)

Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. - Mirjam Schönfeld; Markus Schwiegershausen; Peter Pirsch (VLSI, 1991)

A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes. - Markus Schwiegershausen; Peter Pirsch (EURO-DAC, 1995)

A system level design methodology for the optimization of heterogeneous multiprocessors. - Markus Schwiegershausen; Peter Pirsch (ISSS, 1995)

The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. - Mirjam Schönfeld; Jens Franzen; Markus Schwiegershausen; Peter Pirsch; Uwe Vehlies; Andreas Münzner (J. VLSI Signal Process., 1995)

A system level HW/SW partitioning and optimization tool. - Markus Schwiegershausen; Holger Kropp; Peter Pirsch (EURO-DAC, 1996)

A CAD tool for the optimization of video signal processor architectures. - Holger Kropp; Markus Schwiegershausen; Peter Pirsch (ICASSP, 1996)

Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. - Carsten Reuter; Markus Schwiegershausen; Peter Pirsch (ASAP, 1997)

Implementation of pipelined multipliers on Xilinx FPGAs. - Tien-Toan Do; Holger Kropp; Markus Schwiegershausen; Peter Pirsch (FPL, 1997)

Ein Verfahren zur Optimierung heterogener Multiprozessorsysteme mittels linearer Programmierung. - Markus Schwiegershausen (VDI-Verlag, 1997)