Exploring Loop Scheduling Enhancements in OpenMP: An LLVM Case Study. - Franziska Kasielke; Ronny Tschüter; Christian Iwainsky; Markus Velten; Florina M. Ciorba; Ioana Banicescu (ISPDC, 2019)

Energy Efficiency Aspects of the AMD Zen 2 Architecture. - Robert Schöne; Thomas Ilsche; Mario Bielert; Markus Velten; Markus Schmidl; Daniel Hackenberg (CLUSTER, 2021)

Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. - Markus Velten; Robert Schöne; Thomas Ilsche; Daniel Hackenberg (ICPE, 2022)

Introducing the Arm-Membench Throughput Benchmark. - Cyrill Burth; Markus Velten; Robert Schöne (PPAM (1), 2024)

Energy Efficiency Features of the Intel Alder Lake Architecture. - Robert Schöne; Markus Velten; Daniel Hackenberg; Thomas Ilsche (ICPE, 2024)