PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. - Marta Andronic; George A. Constantinides (ICFPT, 2023)

NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. - Marta Andronic; George A. Constantinides (FPL, 2024)

NeuraLUT-Assemble: Hardware-Aware Assembling of Sub-Neural Networks for Efficient LUT Inference. - Marta Andronic; George A. Constantinides (FCCM, 2025)

Ph.D. Project Hardware-Aware Neural Networks. - Marta Andronic; George A. Constantinides (FCCM, 2025)

ReducedLUT: Table Decomposition with "Don't Care" Conditions. - Oliver Cassidy; Marta Andronic; Samuel Coward; George A. Constantinides (FPGA, 2025)

Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. - Olivia Weng; Marta Andronic; Danial Zuberi; Jiaqing Chen; Caleb Geniesse; George A. Constantinides; Nhan Tran; Nicholas J. Fraser; Javier Mauricio Duarte; Ryan Kastner (FPGA, 2025)

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration. - Yuzong Chen 001; Ahmed F. AbouElhamayed; Xilai Dai; Yang Wang; Marta Andronic; George A. Constantinides; Mohamed S. Abdelfattah (HPCA, 2025)

PolyLUT: Ultra-Low Latency Polynomial Inference With Hardware-Aware Structured Pruning. - Marta Andronic; Jiawen Li; George A. Constantinides (IEEE Trans. Computers, 2025)