Validation of wire length distribution models on commercial designs. - Martijn T. Bennebroek (SLIP, 2003)

Low energy FPGA interconnect design. - Rohini Krishnan; José Pineda de Gyvez; Martijn T. Bennebroek (FPGA, 2004)

A Novel Toolset for the Development of FPGA-like Reconfigurable Logic. - Alexander Danilin; Martijn T. Bennebroek; Sergei Sawitzki (FPL, 2005)

Energy-efficient FPGA interconnect design. - Maurice Meijer; Rohini Krishnan; Martijn T. Bennebroek (DATE Designers' Forum, 2006)

Astra: An Advanced Space-Time Reconfigurable Architecture. - Alexander Danilin; Martijn T. Bennebroek; Sergei Sawitzki (FPL, 2006)

Communication-Centric SoC Debug Using Transactions. - Bart Vermeulen; Kees Goossens; Remco van Steeden; Martijn T. Bennebroek (ETS, 2007)

Multiplexer-based routing fabric for reconfigurable logic. - Martijn T. Bennebroek; Alexander Danilin (FPL, 2007)

Transaction-Based Communication-Centric Debug. - Kees Goossens; Bart Vermeulen; Remco van Steeden; Martijn T. Bennebroek (NOCS, 2007)

A Novel Routing Architecture for Field-Programmable Gate-Arrays. - Alexander Danilin; Martijn T. Bennebroek; Sergei Sawitzki (ARCS, 2008)

Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. - Kees Goossens; Martijn T. Bennebroek; Jae Young Hur; Muhammad Aqeel Wahlah (NOCS, 2008)