Verification of a blind mismatch error equalization method for randomly interleaved ADCs using a 2.5V/12b/30MSs PSAADC. - Martin Anderson; Jonas Elbornsson; Jan-Erik Eklund; Joakim Alvbrant; Henrik Fredriksson (ESSCIRC, 2003)

A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current. - Martin Anderson; Lars Sundström (ESSCIRC, 2007)

Design and Measurement of a CT ΔΣ ADC With Switched-Capacitor Switched-Resistor Feedback. - Martin Anderson; Lars Sundström (IEEE J. Solid State Circuits, 2009)

DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback. - Martin Anderson; Lars Sundström (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators. - Mattias Andersson 003; Martin Anderson; Pietro Andreani; Lars Sundström (ISCAS, 2010)

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution. - Magnus Nilsson; Sven Mattisson; Nikolaus Klemmer; Martin Anderson; Torkel Arnborg; Peter Caputa; Staffan Ek; Lin Fan; Henrik Fredriksson; Fabien Garrigues; Henrik Geis; Hans Hagberg; et al. (ISSCC, 2011)

A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback. - Dejan Radjen; Pietro Andreani; Martin Anderson; Lars Sundström (NORCHIP, 2011)

A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. - Martin Anderson; Roland Strandberg; Staffan Ek; Leif R. Wilhelmsson; Lars Sundström; Mattias Andersson 003; Imad ud Din; Jim Svensson; Thomas Olsson 001; Daniel Eckerbert (ESSCIRC, 2012)

A 9MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression. - Mattias Andersson 003; Martin Anderson; Lars Sundström; Sven Mattisson; Pietro Andreani (ESSCIRC, 2013)

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. - Lars Sundström; Martin Anderson; Roland Strandberg; Staffan Ek; Jim Svensson; Fenghao Mu; Thomas Olsson 001; Imad ud Din; Leif R. Wilhelmsson; Daniel Eckerbert; Sven Mattisson (ISSCC, 2013)

A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier. - Dejan Radjen; Pietro Andreani; Martin Anderson; Lars Sundström (NORCHIP, 2013)

Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation. - Leif R. Wilhelmsson; Jim Svensson; Martin Anderson; Staffan Ek; Roland Strandberg; Lars Sundström (VTC Spring, 2013)

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. - Lars Sundström; Staffan Ek; Jim Svensson; Martin Anderson; Roland Strandberg; Fenghao Mu; Imad ud Din; Thomas Olsson 001; Leif R. Wilhelmsson; Daniel Eckerbert (IEEE J. Solid State Circuits, 2013)

An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS. - Xiaodong Liu; Mattias Andersson 003; Martin Anderson; Lars Sundström; Pietro Andreani (ISCAS, 2014)

A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer. - Dejan Radjen; Martin Anderson; Lars Sundström; Pietro Andreani (NORCHIP, 2014)

A Filtering ΔΣ ADC for LTE and Beyond. - Mattias Andersson 003; Martin Anderson; Lars Sundström; Sven Mattisson; Pietro Andreani (IEEE J. Solid State Circuits, 2014)

A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. - Staffan Ek; Patrik Karlsson; Andreas Kämpe; Roland Strandberg; Aravind Tharayil Narayanan; Martin Anderson; Hind Dafallah; Mesrop Daghbashyan; Tayebeh Ghanavati Nejad; Robert Hägglund; Nikola Ivanisevic; Robert Nilsson; et al. (ESSCIRC, 2022)

A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology. - Mattias Palm; Daniele Mastantuono; Christer Jansson; Erik Backenius; Nikola Ivanisevic; Mikael Normark; Prakash Harikumar; My-Chien Yee; Andreas Leidenhed; Roland Strandberg; Sunny Sharma; Hanie Ghaedrahmati; et al. (ESSCIRC, 2023)