A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS. - Martin Clara; Andreas Wiesbauer; Franz Kuttner (CICC, 2002)

A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. - Andreas Wiesbauer; Martin Clara; Moritz Harteneck; Thomas Pötscher; Berthold Seger; Christoph Sandner; Christian Fleischhacker (IEEE J. Solid State Circuits, 2002)

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. - Susana Patón; Thomas Pötscher; Antonio Di Giandomenico; Klaus Kolhaupt; Luis Hernández 003; Andreas Wiesbauer; Martin Clara; Ramon Frutos (CICC, 2004)

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS. - Dario Giotta; Peter Pessl; Martin Clara; Wolfgang Klatzer; Richard Gaggl (ESSCIRC, 2004)

A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS. - Christoph Sandner; Martin Clara; Andreas Santner; Thomas Hartig; Franz Kuttner (ESSCIRC, 2004)

Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors. - Martin Clara; Andreas Wiesbauer; Wolfgang Klatzer (ISCAS (1), 2004)

A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. - Susana Patón; Antonio Di Giandomenico; Luis Hernández 003; Andreas Wiesbauer; Thomas Pötscher; Martin Clara (IEEE J. Solid State Circuits, 2004)

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS. - Christoph Sandner; Martin Clara; Andreas Santner; Thomas Hartig; Franz Kuttner (IEEE J. Solid State Circuits, 2005)

Clock jitter compensation for current steering DACs. - Andreas Wiesbauer; Dietmar Sträußnigg; Richard Gaggl; Martin Clara; Luis Hernández 003; Daniel Gruber (ISCAS, 2006)

A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS. - Martin Clara; Wolfgang Klatzer; Berthold Seger; Antonio Di Giandomenico; Luca Gori (ISSCC, 2007)

A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS. - Martin Clara; Wolfgang Klatzer; Daniel Gruber; Arnold Marak; Berthold Seger; Wolfgang Pribyl (ESSCIRC, 2008)

Jitter Noise of Sampled Multitone Signals. - Martin Clara; Nicola Da Dalt (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS. - Daniel Gruber; Martin Clara; Berthold Seger (ESSCIRC, 2012)

A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout. - Gil Engel; Martin Clara; Haiyang Zhu; Paul Wilkins (VLSIC, 2015)

10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. - Martin Clara; Daniel Gruber; Albert Molina; Matteo Camponeschi; Yu-shan Wang; Christian Lindholm; Hundo Shin; Ramón Sanchez-Perez; Christoph Duller; Patrick Torta; Kamran Azadet (ISSCC, 2021)

10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. - Daniel Gruber; Martin Clara; Ramón Sanchez-Perez; Yu-shan Wang; Christoph Duller; Gerald Rauter; Patrick Torta; Kamran Azadet (ISSCC, 2021)

A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. - Daniel Gruber; Martin Clara; Ramón Sanchez-Perez; Yu-shan Wang; Christoph Duller; Gerald Rauter; Patrick Torta; Gerhard Knoblinger; Kamran Azadet (IEEE J. Solid State Circuits, 2021)