8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. - Martin Cochet; Alberto Puggelli; Ben Keller; Brian Zimmer; Milovan Blagojevic; Sylvain Clerc; Philippe Roche; Jean-Luc Autran; Borivoje Nikolic (A-SSCC, 2016)

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. - Ben Keller; Martin Cochet; Brian Zimmer; Yunsup Lee; Milovan Blagojevic; Jaehwa Kwak; Alberto Puggelli; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (ESSCIRC, 2016)

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. - Martin Cochet; Sylvain Clerc; Mehdi Naceur; Pierre Schamberger; Damien Croain; Jean-Luc Autran; Philippe Roche (ISCAS, 2016)

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. - Milovan Blagojevic; Martin Cochet; Ben Keller; Philippe Flatresse; Andrei Vladimirescu; Borivoje Nikolic (VLSI Circuits, 2016)

A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. - Martin Cochet; Sylvain Clerc; Guenole Lallement; Fady Abouzeid; Philippe Roche; Jean-Luc Autran (A-SSCC, 2017)

A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Philippe Roche; Jean-Luc Autran (ESSCIRC, 2017)

Very Low Voltage (VLV) Design. - Ramon Bertran; Pradip Bose; David M. Brooks; Jeff Burns; Alper Buyuktosunoglu; Nandhini Chandramoorthy; Eric Cheng; Martin Cochet; Schuyler Eldridge; Daniel Friedman; Hans M. Jacobson; Rajiv V. Joshi; et al. (ICCD, 2017)

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. - Ben Keller; Martin Cochet; Brian Zimmer; Jaehwa Kwak; Alberto Puggelli; Yunsup Lee; Milovan Blagojevic; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (IEEE J. Solid State Circuits, 2017)

A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Philippe Roche; Jean-Luc Autran (IEEE J. Solid State Circuits, 2018)

Resilient Low Voltage Accelerators for High Energy Efficiency. - Nandhini Chandramoorthy; Karthik Swaminathan; Martin Cochet; Arun Paidimarri; Schuyler Eldridge; Rajiv V. Joshi; Matthew M. Ziegler; Alper Buyuktosunoglu; Pradip Bose (HPCA, 2019)

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. - Tianyu Jia; Paolo Mantovani; Maico Cassel dos Santos; Davide Giri; Joseph Zuckerman; Erik Jens Loscalzo; Martin Cochet; Karthik Swaminathan; Gabriele Tombesi; Jeff Jun Zhang; Nandhini Chandramoorthy; John-David Wellman; et al. (ESSCIRC, 2022)

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. - Maico Cassel dos Santos; Tianyu Jia; Martin Cochet; Karthik Swaminathan; Joseph Zuckerman; Paolo Mantovani; Davide Giri; Jeff Jun Zhang; Erik Jens Loscalzo; Gabriele Tombesi; Kevin Tien; Nandhini Chandramoorthy; et al. (ICCAD, 2022)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; John F. Bulzacchelli; Marcel A. Kossel; Pier Andrea Francese; Thomas Morf; Jonathan E. Proesel; Herschel A. Ainspan; Matthias Brändli; Mounir Meghelli (CICC, 2024)

BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs. - Martin Cochet; Karthik Swaminathan; Erik Jens Loscalzo; Joseph Zuckerman; Maico Cassel dos Santos; Davide Giri; Alper Buyuktosunoglu; Tianyu Jia; David Brooks 001; Gu-Yeon Wei; Kenneth L. Shepard; Luca P. Carloni; et al. (ISCA, 2024)

14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. - Maico Cassel dos Santos; Tianyu Jia; Joseph Zuckerman; Martin Cochet; Davide Giri; Erik Jens Loscalzo; Karthik Swaminathan; Thierry Tambe; Jeff Jun Zhang; Alper Buyuktosunoglu; Kuan-Lin Chiu; Giuseppe Di Guglielmo; et al. (ISSCC, 2024)

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1 mathrm{V}_{ text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. - Zeynep Toprak Deniz; Timothy O. Dickson; Martin Cochet; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Matthias Brändli; Thomas Morf; Michael P. Beakes; Mounir Meghelli (VLSI Technology and Circuits, 2024)

A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. - Erik Jens Loscalzo; Martin Cochet; Joseph Zuckerman; Samira Zalias; Michael Lekas; Stephen Cahill; Tianyu Jia; Karthik Swaminathan; Maico Cassel dos Santos; Davide Giri; Hesam Sadeghi; Joseph Meyer; et al. (VLSI Technology and Circuits, 2024)