3DB Challange for DfT, DfM, DOT & BIST Integration into Analogue and Mixed Signal ICs. - Andreas Lechner; Martin John Burbidge; Andrew Richardson 001; B. Hermes (LATW, 2001)

Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops. - Martin John Burbidge; Jim Tijou; Andrew Richardson 001 (DATE, 2003)

Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's. - Martin John Burbidge; Frédéric Poullet; Jim Tijou; Andrew Richardson 001 (J. Electron. Test., 2003)

Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods. - Martin John Burbidge (J. Electron. Test., 2005)

Development of a Remote Access Facility for a PLL Test Course. - Ian Andrew Grout; Jason Murphy; Martin John Burbidge; George Bell; Avril E. Manners (Int. J. Online Eng., 2005)

Evolution of a Remote Access Facility for a PLL Measurement Course. - Martin John Burbidge; Ian Andrew Grout (e-Science, 2006)

Investigation into the Use of Hybrid Solutions for SigmaDelta A/D Converter Testing. - Kostas Georgopoulos; Andreas Lechner; Martin John Burbidge; Andrew Richardson 001 (J. Electron. Test., 2006)

Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods. - Martin John Burbidge; Jim Tijou (Integr., 2007)