Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. - Matthias Beck; Olivier Barondeau; Martin Kaibel; Frank Poehl; Xijiang Lin; Ron Press (DATE, 2005)

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests. - Ivo Koren; Frank Demmerle; Roland May; Martin Kaibel; Sebastian Sattler (ETS, 2007)