Implementation of Realtime and Highspeed Phase Detector on FPGA. - Andre Guntoro; Peter Zipf; Oliver Soffke; Harald Klingbeil; Martin Kumm; Manfred Glesner (ARC, 2006)

Digital hilbert transformers for FPGA-based phase-locked loops. - Martin Kumm; M. Shahab Sanjari (FPL, 2008)

An FPGA-Based Linear All-Digital Phase-Locked Loop. - Martin Kumm; Harald Klingbeil; Peter Zipf (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

High speed low complexity FPGA-based FIR filters using pipelined adder graphs. - Martin Kumm; Peter Zipf (FPT, 2011)

Reduced complexity single and multiple constant multiplication in floating point precision. - Martin Kumm; Katharina Liebisch; Peter Zipf (FPL, 2012)

Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. - Michael Kunz; Martin Kumm; Martin Heide; Peter Zipf (FPL, 2012)

Hybrid multiple constant multiplication for FPGAs. - Martin Kumm; Peter Zipf (ICECS, 2012)

Pipelined adder graph optimization for high speed multiple constant multiplication. - Martin Kumm; Peter Zipf; Mathias Faust; Chip-Hong Chang (ISCAS, 2012)

Multiple constant multiplication with ternary adders. - Martin Kumm; Martin Hardieck; Jens Willkomm; Peter Zipf; Uwe Meyer-Baese (FPL, 2013)

Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. - Martin Kumm; Konrad Möller; Peter Zipf (ISCAS, 2013)

Reconfigurable FIR filter using distributed arithmetic on FPGAs. - Martin Kumm; Konrad Möller; Peter Zipf (ISCAS, 2013)

Dynamically reconfigurable FIR filter architectures with fast reconfiguration. - Martin Kumm; Konrad Möller; Peter Zipf (ReCoSoC, 2013)

FIR filter optimization for video processing on FPGAs. - Martin Kumm; Diana Fanghänel; Konrad Möller; Peter Zipf; Uwe Meyer-Baese (EURASIP J. Adv. Signal Process., 2013)

Pipelined compressor tree optimization using integer linear programming. - Martin Kumm; Peter Zipf (FPL, 2014)

Pipelined reconfigurable multiplication with constants on FPGAs. - Konrad Möller; Martin Kumm; Marco Kleinlein; Peter Zipf (FPL, 2014)

Efficient High Speed Compression Trees on Xilinx FPGAs. - Martin Kumm; Peter Zipf (MBMV, 2014)

Dynamically Reconfigurable Constant Multiplication on FPGAs. - Konrad Möller; Martin Kumm; Björn Barschtipan; Peter Zipf (MBMV, 2014)

An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. - Martin Kumm; Shahid Abbas; Peter Zipf (ARITH, 2015)

Efficient structural adder pipelining in transposed form FIR filters. - Mathias Faust; Martin Kumm; Chip-Hong Chang; Peter Zipf (DSP, 2015)

Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. - Konrad Möller; Martin Kumm; Charles-Frederic Müller; Peter Zipf (CoRR, 2015)

Efficient sum of absolute difference computation on FPGAs. - Martin Kumm; Marco Kleinlein; Peter Zipf (FPL, 2016)

Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". - Martin Kumm; Peter Zipf (Int. J. Reconfigurable Comput., 2016)

CORDIC II: A New Improved CORDIC Algorithm. - Mario Garrido; Petter Kallstrom; Martin Kumm; Oscar Gustafsson (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Multiple constant multiplication optimizations for field programmable gate arrays. - Martin Kumm (Springer Vieweg, 2016)

Resource Optimal Design of Large Multipliers for FPGAs. - Martin Kumm; Johannes Kappauf; Matei Istoan; Peter Zipf (ARITH, 2017)

Model-based hardware design based on compatible sets of isomorphic subgraphs. - Patrick Sittel; Konrad Möller; Martin Kumm; Peter Zipf; Bogdan Pasca 001; Mark Jervis (FPT, 2017)

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. - Patrick Sittel; Martin Kumm; Konrad Möller; Martin Hardieck; Peter Zipf (MBMV, 2017)

Optimization of Constant Matrix Multiplication with Low Power and High Throughput. - Martin Kumm; Martin Hardieck; Peter Zipf (IEEE Trans. Computers, 2017)

Reconfigurable Constant Multiplication for FPGAs. - Konrad Möller; Martin Kumm; Marco Kleinlein; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Karatsuba with Rectangular Multipliers for FPGAs. - Martin Kumm; Oscar Gustafsson; Florent de Dinechin; Johannes Kappauf; Peter Zipf (ARITH, 2018)

ILP-Based Modulo Scheduling and Binding for Register Minimization. - Patrick Sittel; Martin Kumm; Julian Oppermann; Konrad Möller; Peter Zipf; Andreas Koch 001 (FPL, 2018)

Constant Matrix Multiplication with Ternary Adders. - Martin Hardieck; Martin Kumm; Patrick Sittel; Peter Zipf (ICECS, 2018)

ScaLP: A Light-Weighted (MI)LP-Library. - Patrick Sittel; Thomas Schönwälder; Martin Kumm; Peter Zipf (MBMV, 2018)

Advanced Compressor Tree Synthesis for FPGAs. - Martin Kumm; Johannes Kappauf (IEEE Trans. Computers, 2018)

Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. - Konrad Möller; Martin Kumm; Mario Garrido; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Optimal Constant Multiplication Using Integer Linear Programming. - Martin Kumm (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Optimal Single Constant Multiplication Using Ternary Adders. - Martin Kumm; Oscar Gustafsson; Mario Garrido; Peter Zipf (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. - Florent de Dinechin; Silviu-Ioan Filip; Martin Kumm; Luc Forget (ARITH, 2019)

Efficient Error-Tolerant Quantized Neural Network Accelerators. - Giulio Gambardella; Johannes Kappauf; Michaela Blott; Christoph Doehring; Martin Kumm; Peter Zipf; Kees A. Vissers (DFT, 2019)

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. - Julian Oppermann; Patrick Sittel; Martin Kumm; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (Euro-Par, 2019)

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. - Martin Hardieck; Martin Kumm; Konrad Möller; Peter Zipf (FPGA, 2019)

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. - Patrick Sittel; Nicolai Fiege; Martin Kumm; Peter Zipf (ReConFig, 2019)

World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. - Mario Garrido; Konrad Möller; Martin Kumm (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Unrolling Ternary Neural Networks. - Stephen Tridgell; Martin Kumm; Martin Hardieck; David Boland; Duncan J. M. Moss; Peter Zipf; Philip H. W. Leong (ACM Trans. Reconfigurable Technol. Syst., 2019)

Heuristics for the Design of Large Multipliers for FPGAs. - Andreas Böttcher; Keanu Kullmann; Martin Kumm (ARITH, 2020)

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. - Patrick Sittel; John Wickerson; Martin Kumm; Peter Zipf (ASP-DAC, 2020)

Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. - Lukas Sommer; Lukas Weber; Martin Kumm; Andreas Koch 001 (FCCM, 2020)

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. - Julian Faraone; Martin Kumm; Martin Hardieck; Peter Zipf; Xueyuan Liu 002; David Boland; Philip H. W. Leong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Resource Optimal Truncated Multipliers for FPGAs. - Andreas Böttcher; Martin Kumm; Florent de Dinechin (ARITH, 2021)

Towards Arithmetic-Centered Filter Design. - Florent de Dinechin; Silviu-Ioan Filip; Martin Kumm; Anastasia Volkova (ARITH, 2021)

Hardware-Aware Quantization for Multiplierless Neural Network Controllers. - Tobias Habermann; Jonas Kühle; Martin Kumm; Anastasia Volkova (APCCAS, 2022)

Resource Optimal Squarers for FPGAs. - Andreas Böttcher; Martin Kumm; Florent de Dinechin (FPL, 2022)

Truncated Multiple Constant Multiplication with Minimal Number of Full Adders. - Rémi Garcia 002; Anastasia Volkova; Martin Kumm (ISCAS, 2022)

Hardware-Aware Design of Multiplierless Second-Order IIR Filters With Minimum Adders. - Rémi Garcia 002; Anastasia Volkova; Martin Kumm; Alexandre Goldsztejn; Jonas Kühle (IEEE Trans. Signal Process., 2022)

Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. - Anastasia Volkova; Rémi Garcia 002; Florent de Dinechin; Martin Kumm (ACSSC, 2023)

More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. - Martin Hardieck; Tobias Habermann; Fabian Wagner; Michael Mecik; Martin Kumm; Peter Zipf (ISCAS, 2023)

Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders. - Martin Kumm; Anastasia Volkova; Silviu-Ioan Filip (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Towards Globally Optimal Design of Multipliers for FPGAs. - Andreas Böttcher; Martin Kumm (IEEE Trans. Computers, 2023)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs. - Andreas Böttcher; Martin Kumm (ARITH, 2024)

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs. - Andreas Böttcher; Martin Kumm (ASAP, 2024)

Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. - Nicolai Fiege; Martin Kumm; Peter Zipf (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)