A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain 004; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)