A 33MHz 16. Bit Gradient Calculator for Real-Time Volume Imaging. - Martin Margala; Nelson G. Durdle; V. James Raso; Doug L. Hill (Workshop on Graphics Hardware, 1994)

A 33 MHz 16-bit gradient calculator for real-time volume imaging. - Martin Margala; Nelson G. Durdle; Scott Juskiw; V. James Raso; Doug L. Hill (Comput. Graph., 1995)

Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation-a comparative study. - Martin Margala; Nelson G. Durdle (IEEE J. Solid State Circuits, 1998)

Low Power SRAMs for Battery Operation. - Martin Margala (MTDT, 1999)

Low-Power SRAM Circuit Design. - Martin Margala (MTDT, 1999)

Low-Power Memory Circuits. - Martin Margala (The VLSI Handbook, 1999)

I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. - Martin Margala; Srdjan Dragic; Ahmed El-Abasiry; Samuel Ekpe; Viera Stopjaková (IOLTW, 2000)

Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits. - Daniel S. C. Kwok; Martin Margala (ISCAS, 2000)

A novel wide-band CMOS current amplifying cell and its application in power supply current monitoring. - Srdjan Dragic; Igor M. Filanovsky; Martin Margala (ICECS, 2001)

Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. - Brian W. Curran; Mary Gifaldi; Jason Martin; Alper Buyuktosunoglu; Martin Margala; David H. Albonesi (VLSI-SOC, 2001)

Fast and low-power inner product processor. - Natalia Kazakova; Raymond J. Sung; Nelson G. Durdle; Martin Margala; Julien Lamoureux (ISCAS (4), 2001)

Neural Networks-Based Parametric Testing of Analog IC. - Viera Stopjaková; Daniel Micusík; Lubica Benusková; Martin Margala (DFT, 2002)

Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. - Rong Lin; Martin Margala (ACM Great Lakes Symposium on VLSI, 2002)

Minimizing concurrent test time in SoC's by balancing resource usage. - Dan Zhao 001; Shambhu J. Upadhyaya; Martin Margala (ACM Great Lakes Symposium on VLSI, 2002)

Application-specific low-voltage current amplifier for system-on-chip IDDQ test. - Srdjan Dragic; Martin Margala (ICECS, 2002)

Low-voltage analog current detector supporting at-speed BIST. - Srdjan Dragic; Igor M. Filanovsky; Martin Margala (ISCAS (1), 2002)

A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. - Srdjan Dragic; Martin Margala (ISVLSI, 2002)

Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. - Marco S. Dragic; Martin Margala (DFT, 2003)

Control Constrained Resource Partitioning for Complex SoCs. - Dan Zhao 001; Shambhu J. Upadhyaya; Martin Margala (DFT, 2003)

1.8V 0.18µm CMOS Novel Successive Approximation ADC. - Martin Margala; Quentin Diduck; Eric Moule (VLSI-SOC, 2003)

1-V ADPCM Processor for Low-Power Wireless Applications. - Martin Margala; Magdy A. El-Moursy; Ali El-Moursy; Junmou Zhang; Wendi Beth Heinzelman (VLSI-SOC, 2003)

Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters. - Martin Margala; John C. Liobe; Quentin Diduck (VLSI-SOC, 2003)

A versatile built-in CMOS sensing device for digital circuit parametric test. - Marco S. Dragic; Martin Margala (IEEE Trans. Instrum. Meas., 2003)

A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time. - Sadeka Ali; Martin Margala (ISCAS (4), 2004)

6-bit low power low area frequency modulation based flash ADC. - Quentin Diduck; Martin Margala (ISCAS (1), 2004)

Sobel edge detection processor for a real-time volume rendering system. - Natalia Kazakova; Martin Margala; Nelson G. Durdle (ISCAS (2), 2004)

Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. - Karthik Sundararaman; Shambhu J. Upadhyaya; Martin Margala (ISQED, 2004)

A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. - Michael Wieckowski; Martin Margala (SoCC, 2004)

A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems. - Antonija Soldo; Anand Gopalan; P. R. Mukund; Martin Margala (VLSI Design, 2004)

Design of Wireless Sub-Micron Characterization System. - Brian Moore 001; Christopher J. Backhouse; Martin Margala (VTS, 2004)

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks. - Viera Stopjaková; Pavol Malosek; Daniel Micusík; Marek Matej; Martin Margala (J. Electron. Test., 2004)

New approach to design for reusability of arithmetic cores in systems-on-chip. - Martin Margala; Hongfan Wang (Integr., 2004)

A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. - Sadeka Ali; Gregory Briggs; Martin Margala (DFT, 2005)

A New Test Methodology For DNL Error In Flash ADC's. - Michael Wieckowski; John C. Liobe; Quentin Diduck; Martin Margala (DFT, 2005)

A new SoC test architecture with RF/wireless connectivity. - Dan Zhao 001; Shambhu J. Upadhyaya; Martin Margala (ETS, 2005)

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. - Marco Lanuzza; Stefania Perri; Martin Margala; Pasquale Corsonello (FPL, 2005)

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. - Marco Lanuzza; Martin Margala; Pasquale Corsonello (ISLPED, 2005)

A novel five-transistor (5T) sram cell for high performance cache. - Michael Wieckowski; Martin Margala (SoCC, 2005)

A current based self-test methodology for RF front-end circuits. - Anand Gopalan; Martin Margala; P. R. Mukund (Microelectron. J., 2005)

Efficient Addition Circuits for Modular Design of Processors-in-Memory. - Pasquale Corsonello; Stefania Perri; Martin Margala (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Defect detection in analog and mixed circuits by neural networks using wavelet analysis. - Viera Stopjaková; Pavol Malosek; Marek Matej; Vladislav Nagy; Martin Margala (IEEE Trans. Reliab., 2005)

Design of wireless on-wafer submicron characterization system. - Brian Moore 001; Martin Margala; Christopher J. Backhouse (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Adaptable Architectures for Signal Processing Applications. - Martin Margala (AHS, 2006)

New Embedded Core Testing for System-on-Chips and System-in-Packages. - Yuxin Wang; Martin Margala (CCECE, 2006)

On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects. - Yuxin Wang; D. Makadia; Martin Margala (CCECE, 2006)

A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution. - Sadeka Ali; Martin Margala (ISCAS, 2006)

An integrated countermeasure against differential power analysis for secure smart-cards. - Pasquale Corsonello; Stefania Perri; Martin Margala (ISCAS, 2006)

Process tolerant calibration circuit for PLL applications with BIST. - Quentin Diduck; John C. Liobe; Sadeka Ali; Martin Margala (ISCAS, 2006)

A versatile computation module for adaptable multimedia processors. - Yunan Xiang; R. Pettibon; Martin Margala (ISCAS, 2006)

Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs. - Martin Margala (SoCC, 2006)

Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. - Dan Zhao 001; Shambhu J. Upadhyaya; Martin Margala (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (AHS, 2007)

Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. - John C. Liobe; Martin Margala (IOLTS, 2007)

Process and Temperature Calibration of PLLs with BiST Capabilities. - Richard Geisler; John C. Liobe; Martin Margala (ISCAS, 2007)

A Self-Biased Charge-Transfer Sense Amplifier. - Sandeep Patil; Michael Wieckowski; Martin Margala (ISCAS, 2007)

Portless SRAM - A High-Performance Alternative to the 6T Methodology. - Michael Wieckowski; Sandeep Patil; Martin Margala (IEEE J. Solid State Circuits, 2007)

Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits. - John C. Liobe; Martin Margala (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Processor-In-Memory Architecture for Multimedia Compression. - Brandon J. Jasionowski; Michelle K. Lay; Martin Margala (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Digital BIST for Phase-Locked Loops. - Kevin Sliech; Martin Margala (DFT, 2008)

A portless SRAM Cell using stunted wordline drivers. - Michael Wieckowski; Martin Margala (ISCAS, 2008)

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (PATMOS, 2008)

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Pasquale Corsonello (ReConFig, 2008)

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Pasquale Corsonello (SoCC, 2008)

A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops. - John C. Liobe; Richard Geisler; Martin Margala (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. - Sai Rahul Chalamalasetti; Sohan Purohit; Martin Margala; Wim Vanderbauwhede (AHS, 2009)

Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. - Wim Vanderbauwhede; Martin Margala; Sai Rahul Chalamalasetti; Sohan Purohit (ERSA, 2009)

A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. - Sai Rahul Chalamalasetti; Wim Vanderbauwhede; Sohan Purohit; Martin Margala (FPL, 2009)

Study of leakage current mechanisms in ballistic deflection transistors. - Vikas Kaushal; Quentin Diduck; Martin Margala (ACM Great Lakes Symposium on VLSI, 2009)

Varicap threshold logic. - Samed Maltabas; Martin Margala; Ugur Çilingiroglu (ACM Great Lakes Symposium on VLSI, 2009)

A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala (ACM Great Lakes Symposium on VLSI, 2009)

New performance/power/area efficient, reliable full adder design. - Sohan Purohit; Martin Margala; Marco Lanuzza; Pasquale Corsonello (ACM Great Lakes Symposium on VLSI, 2009)

Ballistic Deflection Transistors and the Emerging Nanoscale Era. - David Wolpert 001; Hiroshi Irie; Roman Sobolewski; Paul Ampadu; Quentin Diduck; Martin Margala (ISCAS, 2009)

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (VLSI Design, 2009)

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (J. Low Power Electron., 2009)

Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. - Mohamed El-Hadedy 001; Martin Margala; Danilo Gligoroski; Svein J. Knapskog (IAS, 2010)

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems. - Mohamed El-Hadedy 001; Sohan Purohit; Martin Margala; Svein J. Knapskog (AHS, 2010)

Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala (AHS, 2010)

A C++-embedded Domain-Specific Language for programming the MORA soft processor array. - Wim Vanderbauwhede; Martin Margala; Sai Rahul Chalamalasetti; Sohan Purohit (ASAP, 2010)

A new built-in IDDQ testing method using programmable BICS. - Samed Maltabas; Osman Kubilay Ekekon; Martin Margala (ETS, 2010)

Topology impact on the room temperature performance of THz-range ballistic deflection transistors. - Vikas Kaushal; Ignacio Iñiguez-de-la-Torre; Martin Margala (ACM Great Lakes Symposium on VLSI, 2010)

Design of self correcting radiation hardened digital circuits using decoupled ground bus. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala (ACM Great Lakes Symposium on VLSI, 2010)

Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits. - Osman Kubilay Ekekon; Samed Maltabas; Martin Margala (ISCAS, 2010)

An area efficient design methodology for SEU tolerant digital circuits. - Sohan Purohit; David Harrington; Martin Margala (ISCAS, 2010)

Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. - Mohamed El-Hadedy 001; Martin Margala; Danilo Gligoroski; Svein J. Knapskog (ReConFig, 2010)

Power minimization methodology for VCTL topologies. - Osman Kubilay Ekekon; Samed Maltabas; Martin Margala; Ugur Çilingiroglu (SoCC, 2010)

Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. - Sai Rahul Chalamalasetti; Sohan Purohit; Martin Margala; Wim Vanderbauwhede (IEEE Embed. Syst. Lett., 2010)

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. - Sohan Purohit; Marco Lanuzza; Martin Margala (J. Low Power Electron., 2010)

A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies. - Osman Kubilay Ekekon; Samed Maltabas; Martin Margala (ECCTD, 2011)

A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. - Wim Vanderbauwhede; Sai Rahul Chalamalasetti; Sohan Purohit; Martin Margala (HPCS, 2011)

Evaluating FPGA-acceleration for real-time unstructured search. - Sai Rahul Chalamalasetti; Martin Margala; Wim Vanderbauwhede; Mitch Wright; Parthasarathy Ranganathan (ISPASS, 2012)

Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs. - Kemal Kulovic; Samed Maltabas; Martin Margala (MWSCAS, 2012)

Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability. - Kemal Kulovic; Martin Margala (J. Electron. Test., 2012)

Novel Practical Built-in Current Sensors. - Samed Maltabas; Kemal Kulovic; Martin Margala (J. Electron. Test., 2012)

Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. - Wim Vanderbauwhede; Sai Rahul Chalamalasetti; Martin Margala (Int. J. Reconfigurable Comput., 2012)

Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. - Sohan Purohit; Martin Margala (IEEE Trans. Very Large Scale Integr. Syst., 2012)

High throughput filtering using FPGA-acceleration. - Wim Vanderbauwhede; Anton Frolov 002; Leif Azzopardi; Sai Rahul Chalamalasetti; Martin Margala (CIKM, 2013)

An FPGA memcached appliance. - Sai Rahul Chalamalasetti; Kevin T. Lim; Mitch Wright; Alvin AuYoung; Parthasarathy Ranganathan; Martin Margala (FPGA, 2013)

An IDDQ BIST approach to characterize phase-locked loop parameters. - Samed Maltabas; Osman Kubilay Ekekon; Kemal Kulovic; Anne Meixner; Martin Margala (VTS, 2013)

A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. - Wim Vanderbauwhede; Anton Frolov 002; Sai Rahul Chalamalasetti; Martin Margala (SIGARCH Comput. Archit. News, 2013)

Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Wim Vanderbauwhede (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Wim Vanderbauwhede (IEEE Trans. Very Large Scale Integr. Syst., 2013)

FPGA implementation of low-power split-radix FFT processors. - Zhuo Qian; Nasibeh Nasiri; Oren Segal; Martin Margala (FPL, 2014)

High level programming framework for FPGAs in the data center. - Oren Segal; Martin Margala; Sai Rahul Chalamalasetti; Mitch Wright (FPL, 2014)

A novel low-power and in-place split-radix FFT processor. - Zhuo Qian; Martin Margala (ACM Great Lakes Symposium on VLSI, 2014)

High level programming of FPGAs for HPC and data centric applications. - Oren Segal; Nasibeh Nasiri; Martin Margala; Wim Vanderbauwhede (HPEC, 2014)

Modified fused multiply-accumulate chained unit. - Nasibeh Nasiri; Oren Segal; Martin Margala (MWSCAS, 2014)

Low power RAM-based hierarchical CAM on FPGA. - Zhuo Qian; Martin Margala (ReConFig, 2014)

High Level Programming for Heterogeneous Architectures. - Oren Segal; Martin Margala; Sai Rahul Chalamalasetti; Mitch Wright (CoRR, 2014)

A CMOS ripple detector for integrated voltage regulator testing. - Cagatay Ozmen; Aydin Dirican; Nurettin Tan; Hieu Nguyen 007; Martin Margala (DFTS, 2015)

High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). - Nasibeh Nasiri; Oren Segal; Martin Margala; Wim Vanderbauwhede; Sai Rahul Chalamalasetti (FPGA, 2015)

A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only). - Zhuo Qian; Martin Margala (FPGA, 2015)

Aparapi-UCores: A high level programming framework for unconventional cores. - Oren Segal; Philip Colangelo; Nasibeh Nasiri; Zhuo Qian; Martin Margala (HPEC, 2015)

SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters. - Oren Segal; Philip Colangelo; Nasibeh Nasiri; Zhuo Qian; Martin Margala (CoRR, 2015)

Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits. - Poorna Marthi; Sheikh Rufsan Reza; Nazir Hossain; Jean-François Millithaler; Martin Margala; Ignacio Iñiguez-de-la-Torre; Javier Mateos; Tomás González (ACM Great Lakes Symposium on VLSI, 2016)

Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud. - Oren Segal; Martin Margala (HPCS, 2016)

A new level sensitive D Latch using Ballistic nanodevices. - Poorna Marthi; Nazir Hossain; Jean-François Millithaler; Martin Margala (ISCAS, 2016)

Document classification systems in heterogeneous computing environments. - Nasibeh Nasiri; Philip Colangelo; Oren Segal; Martin Margala; Wim Vanderbauwhede (PATMOS, 2016)

A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems. - Oren Segal; Nasibeh Nasiri; Martin Margala (CoRR, 2016)

A CMOS Ripple Detector for Voltage Regulator Testing. - Hieu Nguyen 007; Cagatay Ozmen; Aydin Dirican; Nurettin Tan; Martin Margala (J. Electron. Test., 2016)

Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. - Poorna Marthi; Nazir Hossain; Huan Wang 009; Jean-François Millithaler; Martin Margala; Ignacio Iñiguez-de-la-Torre; Javier Mateos; Tomás González (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. - Zhuo Qian; Martin Margala (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Column-wise ROIC design with on-chip calibration for photoresistive image sensor. - Cagatay Ozmen; Aydin Dirican; Hieu Nguyen 007; Martin Margala (ECCTD, 2017)

Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. - Philip Colangelo; Randy Huang; Enno Lübbers; Martin Margala; Kevin Nealis (FCCM, 2017)

Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits. - Pilin Junsangsri; Fabrizio Lombardi; Salin Junsangsri; Martin Margala (ACM Great Lakes Symposium on VLSI, 2017)

Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA. - Philip Colangelo; Enno Lübbers; Randy Huang; Martin Margala; Kevin Nealis (HPEC, 2017)

A high performance Full Adder based on Ballistic Deflection Transistor technology. - Poorna Marthi; Nazir Hossain; Huan Wang 009; Jean-François Millithaler; Martin Margala; Ignacio Iñiguez-de-la-Torre; Javier Mateos; Tomás González (ISCAS, 2017)

Sensitivity improvement of a photoresistive image sensor with novel programmable dual element readout and calibration method. - Cagatay Ozmen; Aydin Dirican; Hieu Nguyen 007; Martin Margala (MWSCAS, 2017)

ROIC Design for a 10k Pixel Photoresistive Image Sensor with On-Chip Calibration. - Cagatay Ozmen; Aydin Dirican; Hieu Nguyen 007; Martin Margala (NGCAS, 2017)

Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. - Mohamed El-Hadedy 001; Xinfei Guo; Martin Margala; Mircea R. Stan; Kevin Skadron (J. Signal Process. Syst., 2017)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. - Philip Colangelo; Nasibeh Nasiri; Eriko Nurvitadhi; Asit K. Mishra; Martin Margala; Kevin Nealis (FCCM, 2018)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). - Philip Colangelo; Nasibeh Nasiri; Eriko Nurvitadhi; Asit K. Mishra; Martin Margala; Kevin Nealis (FPGA, 2018)

A droop measurement built-in self-test circuit for digital low-dropout regulators. - Aydin Dirican; Cagatay Ozmen; Martin Margala (ISQED, 2018)

Terahertz travelling wave amplifier design using Ballistic Deflection Transistor. - Huan Wang 009; Jean-François Millithaler; Ronald W. Knepper; Martin Margala (ISQED, 2018)

THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler. - Huan Wang 009; Jean-François Millithaler; Martin Margala; Ronald W. Knepper (NEWCAS, 2018)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. - Philip Colangelo; Nasibeh Nasiri; Asit K. Mishra; Eriko Nurvitadhi; Martin Margala; Kevin Nealis (CoRR, 2018)

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators. - Aydin Dirican; Cagatay Ozmen; Martin Margala (J. Electron. Test., 2018)

5-Gb/s linear re-driver in 180 nm CMOS technology. - Hieu Nguyen 007; Rod Comer; Phuc Pham; Martin Margala (Microelectron. J., 2018)

A Novel Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier System. - Huan Wang 009; Ronald W. Knepper; Jean-François Millithaler; Martin Margala (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms. - Philip Colangelo; Oren Segal; Alexander Speicher; Martin Margala (HPEC, 2019)

Echo Detection Using Differentiation for Compact LIDAR Implementation. - Sharath Patil; Volodymyr Seliuchenko; Darrell Livezey; Saad Ahmad; Bhanu Singh; Martin Margala (MWSCAS, 2019)

Evolutionary Cell Aided Design for Neural Network Architectures. - Philip Colangelo; Oren Segal; Alexander Speicher; Martin Margala (CoRR, 2019)

Automated Hardware and Neural Network Architecture co-design of FPGA accelerators using multi-objective Neural Architecture Search. - Philip Colangelo; Oren Segal; Alexander Speicher; Martin Margala (ICCE-Berlin, 2020)

Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications. - Mohamed El-Hadedy 001; Martin Margala; Sergiu Mosanu; Danilo Gligoroski; Jinjun Xiong; Wen-Mei Hwu (ICECS, 2020)

Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs. - Philip Colangelo; Shayan Sengupta; Martin Margala (ISCAS, 2020)

Functional Safety of a Lidar Sensor System. - Sharath Patil; Bhanu Singh; Darrell Livezey; Saad Ahmad; Martin Margala (MWSCAS, 2020)

AutoML for Multilayer Perceptron and FPGA Co-design. - Philip Colangelo; Oren Segal; Alexander Speicher; Martin Margala (SoCC, 2020)

FPGAs for Domain Experts. - Wim Vanderbauwhede; Sven-Bodo Scholz; Martin Margala (Int. J. Reconfigurable Comput., 2020)

Optimizing open-source FPGA CAD tools. - Shachi Khadilkar; Martin Margala (HPEC, 2022)

Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results. - Sharath Patil; Bhanu Singh; Raunak Borwankar; Martin Margala (NEWCAS, 2022)

Novel Pulse Detection System Using Differentiation: Optical Experimental Results. - Sharath Patil; Bhanu Singh; Raunak Borwankar; Martin Margala (SOCC, 2022)

FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich Neurons. - Uchechukwu Leo Udeji; Martin Margala (SOCC, 2022)

Quantifying the Gap between Open-Source and Vendor FPGA Place and Route Tools. - Shachi Khadilkar; Ahmed Sanaullah; Martin Margala (HPEC, 2023)

RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms. - Mohamed El-Hadedy 001; Russell Hua; Kazutomo Yoshii; Wen-Mei Hwu; Martin Margala (ISQED, 2023)

Optimum Supply Voltage for High Gain Amplifier in Telemetry Circuitry for Ultra-Low Power Implantable Cardiac Pacemaker. - Manisha G; Amit Krishna Dwivedi; V. Uma Maheswari 001; Prasun Chakrabarti; Martin Margala (NEWCAS, 2023)

BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT. - Mohamed El-Hadedy 001; Russell Hua; Shahzman Saqib; Kazutomo Yoshii; Wen-Mei Hwu; Martin Margala (SOCC, 2023)

Prioritized Task-Scheduling Algorithm in Cloud Computing Using Cat Swarm Optimization. - Sudheer Mangalampalli; Sangram Keshari Swain; Tulika Chakrabarti; Prasun Chakrabarti; Ganesh Reddy Karri; Martin Margala; Bhuvan Unhelkar; Sivaneasan Bala Krishnan (Sensors, 2023)

Fault-Tolerant Trust-Based Task Scheduling Algorithm Using Harris Hawks Optimization in Cloud Computing. - Sudheer Mangalampalli; Ganesh Reddy Karri; Amit Gupta; Tulika Chakrabarti; Sri Hari Nallamala; Prasun Chakrabarti; Bhuvan Unhelkar; Martin Margala (Sensors, 2023)

Word2HyperVec: From Word Embeddings to Hypervectors for Hyperdimensional Computing. - Alaaddin Goktug Ayar; Sercan Aygun; M. Hassan Najafi; Martin Margala (ACM Great Lakes Symposium on VLSI, 2024)

Consolidating and Optimizing Embedded Processor IP Blocks for Area, Power, and Sustainability. - Boisy Gene Pitre; Martin Margala; Kevin J. Phillipson; Michael M. Rywalt (IGSC, 2024)

HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator. - Abdullah Sahruri; Martin Margala; Ugur Çilingiroglu (ISQED, 2024)

SegmentAI: A Neural Net Framework for Optimized Multiclass Image Segmentation via FPGA. - Uchechukwu Leo Udeji; Martin Margala (ISVLSI, 2024)

SpikeMotion: A Transformer Framework for High - Throughput Video Segmentation on FPGA. - Uchechukwu Leo Udeji; Martin Margala (MWSCAS, 2024)

IoT-Enabled Advanced Water Quality Monitoring System for Pond Management and Environmental Conservation. - Jeetendra Kumar; Rashmi Gupta; Suvarna Sharma; Tulika Chakrabarti; Prasun Chakrabarti; Martin Margala (IEEE Access, 2024)

Corrections to "Multi Objective Prioritized Workflow Scheduling Using Deep Reinforcement Based Learning in Cloud Computing". - Sudheer Mangalampalli; Syed Shakeel Hashmi; Amit Gupta; Ganesh Reddy Karri; Varada Rajkumar Kukkala; Tulika Chakrabarti; Prasun Chakrabarti; Martin Margala (IEEE Access, 2024)

Multi Objective Prioritized Workflow Scheduling Using Deep Reinforcement Based Learning in Cloud Computing. - Sudheer Mangalampalli; Syed Shakeel Hashmi; Amit Gupta; Ganesh Reddy Karri; Varada Rajkumar Kukkala; Tulika Chakrabarti; Prasun Chakrabarti; Martin Margala (IEEE Access, 2024)

A trust-centric approach to intrusion detection in edge networks for medical internet of thing Ecosystems. - G. Nagarajan; Martin Margala; S. Siva Shankar; Prasun Chakrabarti; R. I. Minu (Comput. Electr. Eng., 2024)

Blockchain-Based Federated Learning Technique for Privacy Preservation and Security of Smart Electronic Health Records. - Manisha Guduri; Chinmay Chakraborty; V. Uma Maheswari 001; Martin Margala (IEEE Trans. Consumer Electron., 2024)

Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing. - Alaaddin Goktug Ayar; Abdullah Sahruri; Sercan Aygun; Mehran Shoushtari Moghadam; M. Hassan Najafi; Martin Margala (IEEE Embed. Syst. Lett., 2024)

Early fire danger monitoring system in smart cities using optimization-based deep learning techniques with artificial intelligence. - P. Dileep Kumar Reddy; Martin Margala; S. Siva Shankar; Prasun Chakrabarti (J. Reliab. Intell. Environ., 2024)

Single-Pass Symbolic Learning for Real-Time Embedded Security. - Alaaddin Goktug Ayar; Sercan Aygun; Martin Margala (ACM Great Lakes Symposium on VLSI, 2025)

HyperEncoding: Spiking Neural Networks with Hyperdimensional Encoding for Robust Edge Intelligence. - Alaaddin Goktug Ayar; Anthony Maida; Martin Margala (ACM Great Lakes Symposium on VLSI, 2025)

Corrections to "IoT-Enabled Advanced Water Quality Monitoring System for Pond Management and Environmental Conservation". - Jeetendra Kumar; Rashmi Gupta; Suvarna Sharma; Tulika Chakrabarti; Prasun Chakrabarti; Martin Margala (IEEE Access, 2025)

Heart disease prediction using spark architecture with fused feature set and hybrid Squeezenet-Linknet model. - Parvathaneni Rajendra Kumar; Prasun Chakrabarti; Tulika Chakrabarti; Bhuvan Unhelkar; Martin Margala (Biomed. Signal Process. Control., 2025)