High Speed and Highly Testable Parallel Two-Rail Code Checker. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DATE, 2003)

Automatic Modification of Sequential Circuits for Self-Checking Implementation. - Cecilia Metra; Stefano Di Francescantonio; Martin Omaña 001 (DFT, 2003)

A Model for Transient Fault Propagation in Combinatorial Logic. - Martin Omaña 001; Giacinto Papasso; Daniele Rossi 001; Cecilia Metra (IOLTS, 2003)

Novel Transient Fault Hardened Static Latch. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (ITC, 2003)

Fault secureness need for next generation high performance microprocessor design for testability structures. - Cecilia Metra; T. M. Mak; Martin Omaña 001 (Conf. Computing Frontiers, 2004)

Are Our Design for Testability Features Fault Secure? - Cecilia Metra; T. M. Mak; Martin Omaña 001 (DATE, 2004)

Fast and Low-Cost Clock Deskew Buffer. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2004)

Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. - José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra (IOLTS, 2004)

Hardware Reconfiguration Scheme for High Availability Systems. - Cecilia Metra; A. Ferrari; Martin Omaña 001; Andrea Pagni (IOLTS, 2004)

Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. - Cecilia Metra; T. M. Mak; Martin Omaña 001 (ITC, 2004)

Model for Transient Fault Susceptibility of Combinational Circuits. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (J. Electron. Test., 2004)

The Other Side of the Timing Equation: a Result of Clock Faults. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (DFT, 2005)

Multiple Transient Faults in Logic: An Issue for Next Generation ICs. - Daniele Rossi 001; Martin Omaña 001; Fabio Toma; Cecilia Metra (DFT, 2005)

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. - José Manuel Cazeaux; Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IOLTS, 2005)

On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. - Martin Omaña 001; O. Losco; Cecilia Metra; Andrea Pagni (IOLTS, 2005)

Low Cost Scheme for On-Line Clock Skew Compensation. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (VTS, 2005)

Low Cost and High Speed Embedded Two-Rail Code Checker. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2005)

Novel on-chip circuit for jitter testing in high-speed PLLs. - José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra (IEEE Trans. Instrum. Meas., 2005)

Advanced techniques for concurrent fault detection. - Martin Omaña 001 (2005)

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. - Martin Omaña 001; José Manuel Cazeaux; Daniele Rossi 001; Cecilia Metra (DATE, 2006)

Can Clock Faults be Detected Through Functional Test? - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; T. M. Mak (DDECS, 2006)

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. - Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; José Manuel Cazeaux; T. M. Mak (IOLTS, 2006)

Checker No-Harm Alarm Robustness. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Andrea Pagni (IOLTS, 2006)

Novel compensation scheme for local clocks of high performance microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (ITC, 2007)

Novel Approach to Clock Fault Testing for High Performance Microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (VTS, 2007)

Latch Susceptibility to Transient Faults and New Hardening Approach. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2007)

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Asifur Rahman; Simon Tam 001 (DFT, 2008)

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; Abhijit Jas; Rajesh Galivanche (ETS, 2008)

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra (J. Electron. Test., 2008)

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. - Martin Omaña 001; Marcin Marzencki; Roberto Specchia; Cecilia Metra; Bozena Kaminska (DFT, 2009)

Novel High Speed Robust Latch. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2009)

Accurate Linear Model for SET Critical Charge Estimation. - Daniele Rossi 001; José Manuel Cazeaux; Martin Omaña 001; Cecilia Metra; Abhijit Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Novel low-cost aging sensor. - Martin Omaña 001; Daniele Rossi 001; Nicolò Bosio; Cecilia Metra (Conf. Computing Frontiers, 2010)

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. - Daniele Rossi 001; Martin Omaña 001; Gianluca Berghella; Cecilia Metra; Abhijit Jas; Chandra Tirumurti; Rajesh Galivanche (Conf. Computing Frontiers, 2010)

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. - Martin Omaña 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Simon Tam 001; Asifur Rahman (DFT, 2010)

Transient Fault and Soft Error On-die Monitoring Scheme. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra (DFT, 2010)

Secure communication protocol for wireless sensor networks. - Daniele Rossi 001; Martin Omaña 001; Daniele Giaffreda; Cecilia Metra (EWDTS, 2010)

High-Performance Robust Latches. - Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (IEEE Trans. Computers, 2010)

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. - Daniele Giaffreda; Martin Omaña 001; Daniele Rossi 001; Cecilia Metra (DFT, 2011)

Impact of Aging Phenomena on Soft Error Susceptibility. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Alessandro Paccagnella (DFT, 2011)

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. - Martin Omaña 001; Cecilia Metra; T. M. Mak; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. - Cristiana Bolchini; Antonio Miele; Chiara Sandionigi; Marco Ottavi; Salvatore Pontarelli; Adelio Salsano; Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; Matteo Sonza Reorda; Luca Sterpone; Massimo Violante; et al. (DFT, 2012)

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. - Martin Omaña 001; Daniele Rossi 001; G. Collepalumbo; Cecilia Metra; Fabrizio Lombardi (DFT, 2012)

New Design for Testability Approach for Clock Fault Testing. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (IEEE Trans. Computers, 2012)

Novel approach to reduce power droop during scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; R. Galivache (ETS, 2013)

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. - Daniele Rossi 001; Martin Omaña 001; G. Garrammone; Cecilia Metra; Abhijit Jas; Rajesh Galivanche (J. Electron. Test., 2013)

Low Cost NBTI Degradation Detection and Masking Approaches. - Martin Omaña 001; Daniele Rossi 001; Nicolò Bosio; Cecilia Metra (IEEE Trans. Computers, 2013)

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Roberto Specchia; Cecilia Metra; Marcin Marzencki; Bozena Kaminska (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power droop reduction during Launch-On-Shift scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (DFT, 2014)

Clock Faults Induced Min and Max Delay Violations. - Daniele Rossi 001; Martin Omaña 001; José Manuel Cazeaux; Cecilia Metra; T. M. Mak (J. Electron. Test., 2014)

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. - Michael A. Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omaña 001; Cecilia Metra; Hans-Joachim Wunderlich (ATS, 2015)

Low-Cost On-Chip Clock Jitter Measurement Scheme. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Asifur Rahman; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. - Daniele Rossi 001; Martin Omaña 001; Daniele Giaffreda; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Impact of Bias Temperature Instability on Soft Error Susceptibility. - Daniele Rossi 001; Martin Omaña 001; Cecilia Metra; Alessandro Paccagnella (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Inverters' self-checking monitors for reliable photovoltaic systems. - Martin Omaña 001; A. Fiore; Cecilia Metra (DATE, 2016)

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandrasekharan Tirumurti; Rajesh Galivanche (IEEE Trans. Computers, 2016)

New Approaches for Power Binning of High Performance Microprocessors. - Martin Omaña 001; Marco Padovani; Kreshnik Veliu; Cecilia Metra; Juergen Alt; Rajesh Galivanche (IEEE Trans. Computers, 2017)

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness. - Martin Omaña 001; TusharaSandeep Edara; Cecilia Metra (IEEE Trans. Emerg. Top. Comput., 2018)

Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers. - Marco Grossi; Martin Omaña 001 (J. Electron. Test., 2019)

Low-Cost Strategy for Bus Propagation Delay Reduction. - Martin Omaña 001; S. Govindaraj; Cecilia Metra (J. Electron. Test., 2019)

Sensors and Embedded Systems in Agriculture and Food Analysis. - Marco Grossi; Annachiara Berardinelli; Edward Sazonov; Wesley Beccaro; Martin Omaña 001 (J. Sensors, 2019)

Fault-Tolerant Inverters for Reliable Photovoltaic Systems. - Martin Omaña 001; Alessandro Fiore; Marco Mongitore; Cecilia Metra (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers. - Marco Grossi; Martin Omaña 001 (J. Electron. Test., 2021)

ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system. - Zahra Shirmohammadi; Ata Khorami; Martin Eugenio Omana (J. Supercomput., 2021)

Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function. - Marco Grossi; Martin Omaña 001; Daniele Rossi 001; Biagio Marzulli; Cecilia Metra (IOLTS, 2022)

Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection. - Fabrizio Finelli; Martin Omaña 001; Cecilia Metra (LATS, 2022)

Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions. - Martin Omaña 001; Sejuti Bardhan; Cecilia Metra (IEEE Trans. Emerg. Top. Comput., 2022)

Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs. - Marco Grossi; Meryem Bouras; Martin Omaña 001; Hassan Berbia (Microprocess. Microsystems, 2022)

RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters. - William Fornaciari; Federico Reghenzani; Federico Terraneo; Davide Baroffio; Cecilia Metra; Martin Omaña 001; Josie E. Rodriguez Condia; Matteo Sonza Reorda; Robert Birke; Iacopo Colonnelli; Gianluca Mittone; Marco Aldinucci; et al. (SAMOS, 2023)

A PCI Express Based Data Acquisition System for the Monitoring of Code Traces of RISC-V Microprocessors. - Marco Grossi; Simone Manoni; Emanuele Parisi; Martin Omaña 001; Cecilia Metra; Fabrizio Alfonsi; Alessandro Gabrielli; Andrea Acquaviva (ICSRS, 2024)

Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches. - Martin Omaña 001; A. Manfredi; Cecilia Metra; R. Locatelli; M. Chiavacci; S. Petrucci (IOLTS, 2024)

Reliability of AI in Predicting the State of Health of Li-Ion Batteries*. - Sara Cretí; Martin Omaña 001; Cecilia Metra; Gianni Borelli (IOLTS, 2024)

On-Line Test of Fully Integrated Voltage Regulators for High Performance Microprocessors of Autonomous Systems. - Martin Omaña 001; A. Menghi; A. Stefani; E. Vicini; Cecilia Metra; G. Froio; S. Petrucci (IOLTS, 2025)

Novel Physical Unclonable Function Implementation for Microcontrollers and Field Programmable Gate Arrays. - Marco Grossi; Martin Omaña 001; Cecilia Metra; Andrea Acquaviva (IEEE Access, 2025)