Martin Omaña

J. Electron. Test., 2013

Novel approach to reduce power droop during scan-based logic BIST.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

New Design for Testability Approach for Clock Fault Testing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Impact of Aging Phenomena on Soft Error Susceptibility.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

High-Performance Robust Latches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Secure communication protocol for wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Transient Fault and Soft Error On-die Monitoring Scheme.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

Novel low-cost aging sensor.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

Accurate Linear Model for SET Critical Charge Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Novel High Speed Robust Latch.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Latch Susceptibility to Transient Faults and New Hardening Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Novel Approach to Clock Fault Testing for High Performance Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Novel compensation scheme for local clocks of high performance microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Checker No-Harm Alarm Robustness.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Can Clock Faults be Detected Through Functional Test?

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Advanced techniques for concurrent fault detection.

[BibT_eX]

[DOI]

PhD thesis, 2005

Novel on-chip circuit for jitter testing in high-speed PLLs.

[BibT_eX]

[DOI]

José Manuel Cazeaux

IEEE Trans. Instrum. Meas., 2005

Low Cost and High Speed Embedded Two-Rail Code Checker.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Low Cost Scheme for On-Line Clock Skew Compensation.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Multiple Transient Faults in Logic: An Issue for Next Generation ICs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

The Other Side of the Timing Equation: a Result of Clock Faults.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Model for Transient Fault Susceptibility of Combinational Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.

[BibT_eX]

[DOI]

T. M. Mak

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Hardware Reconfiguration Scheme for High Availability Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.

[BibT_eX]

[DOI]

José Manuel Cazeaux

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Fast and Low-Cost Clock Deskew Buffer.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Are Our Design for Testability Features Fault Secure?

[BibT_eX]

[DOI]

T. M. Mak

Proceedings of the 2004 Design, 2004

Fault secureness need for next generation high performance microprocessor design for testability structures.

[BibT_eX]

[DOI]

T. M. Mak

Proceedings of the First Conference on Computing Frontiers, 2004

2003

Novel Transient Fault Hardened Static Latch.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Model for Transient Fault Propagation in Combinatorial Logic.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Automatic Modification of Sequential Circuits for Self-Checking Implementation.

[BibT_eX]

[DOI]

Stefano Di Francescantonio

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

High Speed and Highly Testable Parallel Two-Rail Code Checker.

[BibT_eX]

[DOI]