Through silicon via to FinFET noise coupling in 3-D integrated circuits. - A. Rouhi Najaf Abadi; W. Guo; X. Sun; K. Ben Ali; Jean-Pierre Raskin; Martin Rack; C. Roda Neve; M. Choi; V. Moroz; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; et al. (ICICDT, 2015)

Impact of III-N buffer layers on RF losses and harmonic distortion of GaN-on-Si Substrates. - Pieter Cardinael; Sachin Yadav 001; Ming Zhao; Martin Rack; Dimitri Lederer; Nadine Collaert; Bertrand Parvais; Jean-Pierre Raskin (ESSDERC, 2021)

High-Temperature Characterization of Novel Silicon-Based Substrate Solutions for RF-IC Applications. - Quentin Courte; Martin Rack; M. Nabet; Pieter Cardinael; Jean-Pierre Raskin (ESSDERC, 2021)

Impact of Device Shunt Loss on DC-80 GHz SPDT in 22 nm FD-SOI. - Martin Rack; Lucas Nyssens; Quentin Courte; Dimitri Lederer; Jean-Pierre Raskin (ESSDERC, 2021)

Substrate noise mitigation using high resistivity base silicon wafer for a 14 GHz VCO on 28 nm FD-SOI. - Youssef Bendou; Martin Rack; Dimitri Lederer; Andreia Cathelin; Jean-Pierre Raskin (NEWCAS, 2023)

Analysis of Back-Gate Bias Control on EVM Measurements of a Dual-Band Power Amplifier in 22 nm FD-SOI for 5G 28 and 39 GHz Applications. - Lucas Nyssens; M. Nabet; Martin Rack; Youssef Bendou; Sidina Wane; Jacques Sombrin; Jean-Pierre Raskin; Dimitri Lederer (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)