Development of a Telephone Answering Machine in a Lab - FPGAs in Education. - Guido Schumacher; Bernhard Josko; Gerhard Wagner; Martin Radetzki (FPL, 1996)

ATM Cell Modelling using Objective VHDL. - Alberto Allara; Massimo Bombana; Patrizia Cavalloro; Wolfgang Nebel; Wolfram Putzke-Röming; Martin Radetzki (ASP-DAC, 1998)

A Flexible Message Passing Mechanism for Objective VHDL. - Wolfram Putzke-Röming; Martin Radetzki; Wolfgang Nebel (DATE, 1998)

Übersetzung von Objektorientiertem VHDL nach Standard VHDL. - Martin Radetzki; Wolfram Putzke-Röming; Wolfgang Nebel (MBMV, 1998)

A Unified Approach to Object-Oriented VHDL. - Martin Radetzki; Wolfram Putzke-Röming; Wolfgang Nebel (J. Inf. Sci. Eng., 1998)

Data Type Analysis for Hardware Synthesis from Object-Oriented Models. - Martin Radetzki; Ansgar Stammermann; Wolfram Putzke-Röming; Wolfgang Nebel (DATE, 1999)

Synthesis of digital circuits from object oriented specifications. - Martin Radetzki (2000)

A Qualification Platform for Design Reuse. - Ralf Seepold; Natividad Martínez Madrid; Andreas Vörg; Wolfgang Rosenstiel; Martin Radetzki; Peter Neumann; Jürgen Haase (ISQED, 2002)

Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions). - Martin Radetzki (Informationstechnik Tech. Inform., 2002)

sciPROVE: C++ Based Verification Environment for IP and SoC Design1. - U. Badelt; H. Kühl; Martin Radetzki (FDL, 2003)

Measurement of IP Qualification Costs and Benefits. - Andreas Vörg; Martin Radetzki; Wolfgang Rosenstiel (DATE, 2004)

IPQ: IP Qualification for Efficient System Design. - Hans-Jürgen Brand; Steffen Rülke; Martin Radetzki (ISQED, 2004)

Intelligent IP retrieval driven by application requirements. - Martin Schaaf; Andrea Freßmann; Rainer Maximini; Ralph Bergmann; Alexander Tartakovski; Martin Radetzki (Integr., 2004)

SystemC TLM Transaction Modelling and Dispatch for Active Object. - Martin Radetzki (FDL, 2006)

Modelling Alternatives for Cycle Approximate Bus TLMs. - Martin Radetzki; Rauf Salimi Khaligh (FDL, 2007)

Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. - Rauf Salimi Khaligh; Martin Radetzki (IESS, 2007)

Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. - Martin Radetzki (MBMV, 2007)

Accuracy-Adaptive Simulation of Transaction Level Models. - Martin Radetzki; Rauf Salimi Khaligh (DATE, 2008)

A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. - Rauf Salimi Khaligh; Martin Radetzki (FDL, 2008)

Adaptive Interconnect Models for Transaction-Level Simulation. - Rauf Salimi Khaligh; Martin Radetzki (FDL (Selected Papers), 2008)

A data traffic efficient H.264 deblocking IP. - Weining Hao; Martin Radetzki (ISCAS, 2008)

Test exploration and validation using transaction level models. - Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo; Paolo Prinetto (DATE, 2009)

A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. - Adán Kohler; Martin Radetzki (FDL, 2009)

Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. - Rauf Salimi Khaligh; Martin Radetzki (IESS, 2009)

Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. - Adán Kohler; Martin Radetzki (MBMV, 2009)

Fault-tolerant architecture and deflection routing for degradable NoC switches. - Adán Kohler; Martin Radetzki (NOCS, 2009)

An intelligent deflection router for networks-on-chip. - Martin Radetzki; Adán Kohler (WISES, 2009)

Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. - Rauf Salimi Khaligh; Martin Radetzki (DATE, 2010)

A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. - Rauf Salimi Khaligh; Martin Radetzki (FDL, 2010)

Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). - Gert Schley; Martin Radetzki; Adán Kohler (it Inf. Technol., 2010)

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. - Adán Kohler; Gert Schley; Martin Radetzki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Efficient Fault Simulation of SystemC Designs. - Weiyun Lu; Martin Radetzki (DSD, 2011)

Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. - Bastian Haetzer; Gert Schley; Rauf Salimi Khaligh; Martin Radetzki (WESE, 2011)

Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. - Martin Radetzki (EUC, 2011)

A case study on message-based discrete event simulation for Transaction Level Modeling. - Bastian Haetzer; Martin Radetzki (FDL, 2011)

A metamodel and semantics for transaction level modeling. - Rauf Salimi Khaligh; Martin Radetzki (FDL, 2011)

Optimal distribution of privileged nodes in networks-on-chip. - Gert Schley; Martin Radetzki (WISES, 2011)

Cost-Based Deflection Routing for Intelligent NoC Switches. - Martin Radetzki; Adán Kohler (Solutions on Embedded Systems, 2011)

Low-Latency Collectives for the Intel SCC. - Adán Kohler; Martin Radetzki; Philipp Gschwandtner; Thomas Fahringer (CLUSTER, 2012)

Minimal MPI as programming interface for multicore System-on-Chips. - Adán Kohler; Juan Manuel Castillo-Sanchez; Joachim Gross; Martin Radetzki (FDL, 2012)

Optimized Reduce for Mesh-Based NoC Multiprocessors. - Adán Kohler; Martin Radetzki (IPDPS Workshops, 2012)

Latency-optimized Collectives for High Performance on Intel's Single-chip Cloud Computer. - Adán Kohler; Martin Radetzki (MARC@RWTH, 2012)

Semantics and efficient simulation of accuracy-adaptive TLMs. - Rauf Salimi Khaligh; Martin Radetzki (Des. Autom. Embed. Syst., 2012)

Platform based design. - Jean-Philippe Babau; Martin Radetzki (FDL, 2013)

Fine grained adaptive simulation with application to NoCs. - Marcus Eggenberger; Martin Radetzki (FDL, 2013)

Systemc transaction level modeling with transaction events. - Bastian Haetzer; Martin Radetzki (FDL, 2013)

Simulation analysis and validation. - Frank Oppenheimer; Martin Radetzki (FDL, 2013)

Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. - Adán Kohler; Martin Radetzki (GreenCom/iThings/CPScom, 2013)

Scalable parallel simulation of networks on chip. - Marcus Eggenberger; Martin Radetzki (NOCS, 2013)

Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. - Gert Schley; Nikolaos Batzolis; Martin Radetzki (PDP, 2013)

Methods for fault tolerance in networks-on-chip. - Martin Radetzki; Chaochao Feng; Xueqian Zhao; Axel Jantsch (ACM Comput. Surv., 2013)

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. - Khalid Latif 002; Amir-Mohammad Rahmani; Ethiopia Nigussie; Tiberiu Seceleanu; Martin Radetzki; Hannu Tenhunen (J. Electron. Test., 2013)

Optimal placement of vertical connections in 3D Network-on-Chip. - Thomas Canhao Xu; Gert Schley; Pasi Liljeberg; Martin Radetzki; Juha Plosila; Hannu Tenhunen (J. Syst. Archit., 2013)

Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. - Weiyun Lu; Martin Radetzki (Microprocess. Microsystems, 2013)

On Covering Structural Defects in NoCs by Functional Tests. - Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki; Hans-Joachim Wunderlich (ATS, 2014)

SystemC AMS power electronic modeling with ideal instantaneous switches. - Leandro Gil; Martin Radetzki (FDL, 2014)

A comparison of parallel systemc simulation approaches at RTL. - Bastian Haetzer; Martin Radetzki (FDL, 2014)

Asynchronous parallel simulation with transaction events. - Bastian Haetzer; Martin Radetzki (ICSAMOS, 2014)

Editorial introduction - Special issue on languages, models and model based design for embedded systems. - Martin Radetzki; Axel Jantsch (Des. Autom. Embed. Syst., 2014)

Multi-Layer Test and Diagnosis for Dependable NoCs. - Hans-Joachim Wunderlich; Martin Radetzki (NOCS, 2015)

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. - Gert Schley; Martin Radetzki (PDP, 2015)

Optimal memory selection for low power embedded systems. - Marcus Eggenberger; Martin Radetzki (WISES, 2015)

Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. - Leandro Gil; Martin Radetzki (DATE, 2016)

Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. - Marcus Eggenberger; Manuel Strobel; Martin Radetzki (PDP, 2016)

Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. - Gert Schley; Ibrahim Ahmed 001; Muhammad Afzal; Martin Radetzki (Comput. Electr. Eng., 2016)

Semi-symbolic operational computation for robust control system design. - Leandro Gil; Martin Radetzki (MMAR, 2017)

Hybrid instruction set simulation for fast and accurate memory access profiling. - Manuel Strobel; Martin Radetzki (WISES, 2017)

Low power memory allocation and mapping for area-constrained systems-on-chips. - Manuel Strobel; Marcus Eggenberger; Martin Radetzki (EURASIP J. Embed. Syst., 2017)

Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. - Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich; Martin Radetzki (IEEE Trans. Computers, 2017)

Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. - Jie Hou 002; Martin Radetzki (PDP, 2018)

Combined MPSoC Task Mapping and Memory Optimization for Low-Power. - Manuel Strobel; Gereon Führ; Martin Radetzki; Rainer Leupers (APCCAS, 2019)

A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms. - Jie Hou 002; Martin Radetzki (FDL, 2019)

A Backend Tool for the Integration of Memory Optimizations into Embedded Software. - Manuel Strobel; Martin Radetzki (FDL, 2019)

Automated Sensor Firmware Development - Generation, Optimization, and Analysis. - Jens Rudolf; Manuel Strobel; Joscha Benz; Christian Haubelt; Martin Radetzki; Oliver Bringmann 001 (MBMV, 2019)

A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. - Jie Hou 002; Qi Han 006; Martin Radetzki (MCSoC, 2019)

Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems. - Manuel Strobel; Martin Radetzki (MCSoC, 2019)

Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design. - Manuel Strobel; Martin Radetzki (ACM Trans. Embed. Comput. Syst., 2019)

Comprehensive modeling and evaluation of Network-on-Chip performability. - Jie Hou 002; Martin Radetzki (MBMV, 2021)

Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming. - Shuang Liu 009; Martin Radetzki (MCSoC, 2023)

Synergistic Floorplanning and Routing Topology Co-design for Application-Specific NoC Synthesis. - Shuang Liu 009; Martin Radetzki (MCSoC, 2024)

Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based Systems. - Shuang Liu 009; Martin Radetzki (SOCC, 2024)