On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. - Martin Saint-Laurent; Madhavan Swaminathan; James D. Meindl (ICCD, 2001)

Optimal Sequencing Energy Allocation for CMOS Integrated Systems. - Martin Saint-Laurent; Vojin G. Oklobdzija; Simon S. Singh; Madhavan Swaminathan (ISQED, 2002)

Modeling and Analysis of High-Frequency Microprocessor Clocking Networks. - Martin Saint-Laurent (2005)

A 65-nm pulsed latch with a single clocked transistor. - Martin Saint-Laurent; Baker Mohammad; Paul Bassett (ISLPED, 2007)

A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures. - Martin Saint-Laurent (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Cache Design for Low Power and High Yield. - Baker Mohammad; Martin Saint-Laurent; Paul Bassett; Jacob A. Abraham (ISQED, 2008)

A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. - Martin Saint-Laurent; Animesh Datta (ISLPED, 2010)

Energy efficient design techniques for a digital signal processor. - Paul Bassett; Martin Saint-Laurent (ICICDT, 2012)

10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications. - Martin Saint-Laurent; Paul Bassett; Ken Lin; Yuhe Wang; Son Le; Xufeng Chen; Maen Alradaideh; Tom Wernimont; Kartik Ayyar; Dan Bui; Dwight Galbi; Allan Lester; et al. (ISSCC, 2014)

Power-aware multi-voltage custom memory models for enhancing RTL and low power verification. - Vijay Kiran Kalyanam; Martin Saint-Laurent; Jacob A. Abraham (ICCD, 2015)

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. - N. N. Mojumder; Seung Chul Song; K. Rim; J. Xu; Joseph Wang; J. Zhu; Milena Vratonjic; K. Lin; Martin Saint-Laurent; Paul Bassett; Geoffrey Yeap (VLSIC, 2015)

A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications. - Martin Saint-Laurent; Paul Bassett; Ken Lin; Baker Mohammad; Yuhe Wang; Xufeng Chen; Maen Alradaideh; Tom Wernimont; Kartik Ayyar; Dan Bui; Dwight Galbi; Allan Lester; et al. (IEEE J. Solid State Circuits, 2015)